CODEWITHSUNDEEP
cgccmakefiledependencies
u185619
u185619

Reputation: 287

how to use gcc -M for autodependency generator

I got a advice on code review to use -M options family with gcc to generate auto dependency generation the problem is that the documentation is confusing me and I still dont understand how am I supposed to use it when I simply added -M to CFLAGS the and still I could barely find any difference I just got the warning: main.o: linker input file unused because linking not done I am using gcc 4.8.4

Upvotes: 0

Views: 1201

Answers (2)

user2371524
user2371524

Reputation:

For a fully automatic version that doesn't interfere with "clean" targets, use something like this:

%.d: %.c Makefile
    $(CC) -MM -MT"$@ $(@:.d=.o)" -MF$@ $(CFLAGS) $(INCLUDES) $<

ifneq ($(MAKECMDGOALS),clean)
ifneq ($(MAKECMDGOALS),distclean)
-include $(OBJS:.o=.d)
endif
endif

This assumes you have a list of object files to be linked in $(OBJS). The -MT parameter here makes sure that the dependency file itself will have the same dependencies as the object file. Without it, the generated dependency file would e.g. look like

foo.o: foo.c foo.h bar.h

but you want

foo.o foo.d: foo.c foo.h bar.h

so dependencies are also recreated when you change source.

This scheme of doing it doesn't change your rule to create the object files, dependencies are generated in an extra compiler invocation. There are also alternatives doing both code and dependency generation in a single run. The above is what I like to use.

Upvotes: 2

Tom Tromey
Tom Tromey

Reputation: 22569

It's not enough to change how you invoke the compiler -- you also have to change your Makefile to make use of the newly-generated information.

Paul Smith wrote a good guide to how to set up automatic dependency tracking for make.

Upvotes: 3

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