CODEWITHSUNDEEP
calgorithmflash-memory
Ivan
Ivan

Reputation: 21

Does YAFFS filesystem support ECC more than 1 bit per 256 byte page?

From YAFFS2 source (yaffs_ecc.c): "The ECC can correct single bit errors in a 256-byte page of data."

But some flash memory requires ECC code, that, for example, must correct 8 bit per 540 byte, or 4 bit per 528 bytes, etc.

Can ECC algorithm from YAFFS correct more than 1 error? Please give me link on ECC algorithm realization, that can correct more than 1 error and work fastest.

Upvotes: 2

Views: 488

Answers (1)

Dilip Kumar
Dilip Kumar

Reputation: 1746

YAFFS is Nand based file system. The file system is designed based on the architecture of the nand flashes.

Can ECC algorithm from YAFFS correct more than 1 error?

No it cant correct more than 1 bit error.

As per the nand architecture for every page one ECC is maintained and it can handle up-to 1-bit error. If ECC shows more than 2 bit error then its un-correctable error and the page is marked bad block.

Even if you try to implement an ECC algorithm in yaffs the flash memory will not be able to be handle the error correction. Spare area will be maintained in the flash to store the ECC bits and there is limited number of bytes to store this data.

In order to modify the file system you can check the data sheet of the flash you are trying to implement. And most of the flash has internal ECC generation controller i.e hardware controller.

can correct 8 bit per 540 byte?

It will be too complex to implement such an algorithm for flash.

Here are the some of the ECC algorithms used for flash memories

  1. Hamming Algorithm
  2. Reed-Solomon Algorithm
  3. Bose-Chaudhuri-Hocquenghem (BCH) algorithm

There is possibity of correcting more errors using BCH algorithm this algorithm is implemented mostly in hardware controller

Upvotes: 1

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