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Andy J
Andy J

Reputation: 1545

NAND ECC sector size

Recently I have been studying the basics of Hamming, R-S and BCH ECC schemes for NAND flash.

According to this source (at the bottom of the page), for BCH, you could have a sector size of 512B or 1024B. The number of parity bits depends on the sector size.

My question -- When dealing with ECC, is the sector size (512B or 1024B) "user selectable"? That is, selectable by the software programmer? Or is this something set in stone by the NAND vendor that you must comply with?

Upvotes: 1

Views: 1410

Answers (2)

johny
johny

Reputation: 21

Yes, ECC sector size is user selectable. Here 'the user' is one who has full control over 'the programmer' you mentioned. Selection of ECC page size is not restricted from the NAND flash perspective. But, it always depends on ‘the programmer’ which is going to communicate with NAND to put/read data. The ‘programmer’ can be a micro controller in an embedded device(like cellphone, Set-top Box etc.), a PC based NAND bulk programmer device etc. With respect to the design/design restriction of ‘the programmer’, it may want to select any one of the ECC page size.

NAND flsh does not restricts the aspects like, the format/size/orentation of ECC data to page data.

Upvotes: 2

abarisone
abarisone

Reputation: 3783

I found a very good resource about How to use NAND flash related to STMicroelectronics products that can give you some hints.

For example in the above mentioned NAND flash:

The BCH Controller uses ECC sectors of 1024 bytes, which means Small Page NAND (512B) is not supported.

Have also a look to these tools created for interacting with NAND devices.

Upvotes: 1

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