NIOS II - Resetting FPGA from software (reload FPGA configuration, don't just reset processor)

Question

Context

I'm writing code that runs in uClinux on a NIOS II processor. The FPGA is a Stratix II. The FPGA design was done by someone else who is no longer at the company and I'm not a firmware designer, just a software programmer.

Problem

The FPGA loads its configuration from a flash device on power-up. I've written a app that re-programs the flash, but I need to find a way to cause it to re-load the FPGA configuration, and I need to do it from software. Currently the only way to get the FPGA to reload is to cycle the power, but that's not possible in the customer's environment.

The language I'm writing in isn't really relevant, suffice to say that I can easily write to a hardware register at a known address, for example in Tcl: nioswr32 $reg_addr $value What I'm trying to find is some sort of reset register I can use. Maybe a JTAG interface? I found reference to a JTAG_UART, but apparently that's just for providing console functionality through JTAG. Maybe there's a hardware watchdog timer I can mess with?

Note that I'm not just trying to reset the NIOS processor. I can easily do that using busybox, but that won't reload the FPGA firmware.

Below is a copy of my system.h header which I believe was generated by SOPC Builder, so you can see what resources are available.

#ifndef __SYSTEM_H_
#define __SYSTEM_H_

/*

DO NOT MODIFY THIS FILE

   Changing this file will have subtle consequences
   which will almost certainly lead to a nonfunctioning
   system. If you do modify this file, be aware that your
   changes will be overwritten and lost when this file
   is generated again.

DO NOT MODIFY THIS FILE

*/

/******************************************************************************
*                                                                             *
* License Agreement                                                           *
*                                                                             *
* Copyright (c) 2003 Altera Corporation, San Jose, California, USA.           *
* All rights reserved.                                                        *
*                                                                             *
* Permission is hereby granted, free of charge, to any person obtaining a     *
* copy of this software and associated documentation files (the "Software"),  *
* to deal in the Software without restriction, including without limitation   *
* the rights to use, copy, modify, merge, publish, distribute, sublicense,    *
* and/or sell copies of the Software, and to permit persons to whom the       *
* Software is furnished to do so, subject to the following conditions:        *
*                                                                             *
* The above copyright notice and this permission notice shall be included in  *
* all copies or substantial portions of the Software.                         *
*                                                                             *
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR  *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,    *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER      *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING     *
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER         *
* DEALINGS IN THE SOFTWARE.                                                   *
*                                                                             *
* This agreement shall be governed in all respects by the laws of the State   *
* of California and by the laws of the United States of America.              *
*                                                                             *
******************************************************************************/

/*
 * system configuration
 *
 */

#define ALT_SYSTEM_NAME "nios_application"
#define ALT_CPU_NAME "app_CPU"
#define ALT_CPU_ARCHITECTURE "altera_nios2"
#define ALT_DEVICE_FAMILY "STRATIXII"
#define ALT_STDIN "/dev/JTAG_UART"
#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
#define ALT_STDIN_BASE 0x03000100
#define ALT_STDIN_DEV JTAG_UART
#define ALT_STDIN_PRESENT
#define ALT_STDOUT "/dev/JTAG_UART"
#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"
#define ALT_STDOUT_BASE 0x03000100
#define ALT_STDOUT_DEV JTAG_UART
#define ALT_STDOUT_PRESENT
#define ALT_STDERR "/dev/JTAG_UART"
#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
#define ALT_STDERR_BASE 0x03000100
#define ALT_STDERR_DEV JTAG_UART
#define ALT_STDERR_PRESENT
#define ALT_CPU_FREQ 100000000
#define ALT_IRQ_BASE NULL

/*
 * processor configuration
 *
 */

#define NIOS2_CPU_IMPLEMENTATION "fast"
#define NIOS2_BIG_ENDIAN 0

#define NIOS2_ICACHE_SIZE 4096
#define NIOS2_DCACHE_SIZE 0
#define NIOS2_ICACHE_LINE_SIZE 32
#define NIOS2_ICACHE_LINE_SIZE_LOG2 5
#define NIOS2_DCACHE_LINE_SIZE 0
#define NIOS2_DCACHE_LINE_SIZE_LOG2 0
#define NIOS2_FLUSHDA_SUPPORTED

#define NIOS2_EXCEPTION_ADDR 0x20000020
#define NIOS2_RESET_ADDR 0x00260000
#define NIOS2_BREAK_ADDR 0x03000820

#define NIOS2_HAS_DEBUG_STUB

#define NIOS2_CPU_ID_SIZE 1
#define NIOS2_CPU_ID_VALUE 0

/*
 * A define for each class of peripheral
 *
 */

#define __ALTERA_AVALON_JTAG_UART
#define __ALTERA_AVALON_NEW_SDRAM_CONTROLLER
#define __ALTERA_AVALON_TRI_STATE_BRIDGE
#define __ALTERA_AVALON_CFI_FLASH
#define __ALTERA_AVALON_PIPELINE_BRIDGE
#define __ALTERA_AVALON_TIMER
#define __ALTERA_AVALON_UART
#define __SPI16
#define __ALTERA_AVALON_PIO
#define __I2C8
#define __PBRIDGE
#define __ALTERA_NIOS_CUSTOM_INSTR_ENDIAN_CONVERTER
#define __ALTERA_NIOS_CUSTOM_INSTR_INTERRUPT_VECTOR

/*
 * JTAG_UART configuration
 *
 */

#define JTAG_UART_NAME "/dev/JTAG_UART"
#define JTAG_UART_TYPE "altera_avalon_jtag_uart"
#define JTAG_UART_BASE 0x03000100
#define JTAG_UART_SPAN 8
#define JTAG_UART_IRQ 1
#define JTAG_UART_WRITE_DEPTH 64
#define JTAG_UART_READ_DEPTH 64
#define JTAG_UART_WRITE_THRESHOLD 8
#define JTAG_UART_READ_THRESHOLD 8
#define JTAG_UART_READ_CHAR_STREAM ""
#define JTAG_UART_SHOWASCII 1
#define JTAG_UART_READ_LE 0
#define JTAG_UART_WRITE_LE 0
#define JTAG_UART_ALTERA_SHOW_UNRELEASED_JTAG_UART_FEATURES 0
#define ALT_MODULE_CLASS_JTAG_UART altera_avalon_jtag_uart

/*
 * SDRAM configuration
 *
 */

#define SDRAM_NAME "/dev/SDRAM"
#define SDRAM_TYPE "altera_avalon_new_sdram_controller"
#define SDRAM_BASE 0x20000000
#define SDRAM_SPAN 16777216
#define SDRAM_REGISTER_DATA_IN 1
#define SDRAM_SIM_MODEL_BASE 0
#define SDRAM_SDRAM_DATA_WIDTH 32
#define SDRAM_SDRAM_ADDR_WIDTH 12
#define SDRAM_SDRAM_ROW_WIDTH 12
#define SDRAM_SDRAM_COL_WIDTH 8
#define SDRAM_SDRAM_NUM_CHIPSELECTS 1
#define SDRAM_SDRAM_NUM_BANKS 4
#define SDRAM_REFRESH_PERIOD 15.625
#define SDRAM_POWERUP_DELAY 200.0
#define SDRAM_CAS_LATENCY 2
#define SDRAM_T_RFC 70.0
#define SDRAM_T_RP 20.0
#define SDRAM_T_MRD 6
#define SDRAM_T_RCD 20.0
#define SDRAM_T_AC 5.5
#define SDRAM_T_WR 16.0
#define SDRAM_INIT_REFRESH_COMMANDS 2
#define SDRAM_INIT_NOP_DELAY 0.0
#define SDRAM_SHARED_DATA 0
#define SDRAM_SDRAM_BANK_WIDTH 2
#define SDRAM_TRISTATE_BRIDGE_SLAVE ""
#define SDRAM_STARVATION_INDICATOR 0
#define SDRAM_IS_INITIALIZED 1
#define ALT_MODULE_CLASS_SDRAM altera_avalon_new_sdram_controller

/*
 * FLASH_BRIDGE configuration
 *
 */

#define FLASH_BRIDGE_NAME "/dev/FLASH_BRIDGE"
#define FLASH_BRIDGE_TYPE "altera_avalon_tri_state_bridge"
#define ALT_MODULE_CLASS_FLASH_BRIDGE altera_avalon_tri_state_bridge

/*
 * CFI_FLASH configuration
 *
 */

#define CFI_FLASH_NAME "/dev/CFI_FLASH"
#define CFI_FLASH_TYPE "altera_avalon_cfi_flash"
#define CFI_FLASH_BASE 0x00000000
#define CFI_FLASH_SPAN 16777216
#define CFI_FLASH_SETUP_VALUE 0
#define CFI_FLASH_WAIT_VALUE 0
#define CFI_FLASH_HOLD_VALUE 0
#define CFI_FLASH_TIMING_UNITS "ns"
#define CFI_FLASH_UNIT_MULTIPLIER 1
#define CFI_FLASH_SIZE 16777216
#define ALT_MODULE_CLASS_CFI_FLASH altera_avalon_cfi_flash

/*
 * BRIDGE configuration
 *
 */

#define BRIDGE_NAME "/dev/BRIDGE"
#define BRIDGE_TYPE "altera_avalon_pipeline_bridge"
#define BRIDGE_BASE 0x04000000
#define BRIDGE_SPAN 256
#define BRIDGE_IS_DOWNSTREAM 1
#define BRIDGE_IS_UPSTREAM 0
#define BRIDGE_IS_WAITREQUEST 0
#define BRIDGE_ENABLE_ARBITERLOCK 0
#define ALT_MODULE_CLASS_BRIDGE altera_avalon_pipeline_bridge

/*
 * TIMER configuration
 *
 */

#define TIMER_NAME "/dev/TIMER"
#define TIMER_TYPE "altera_avalon_timer"
#define TIMER_BASE 0x04000000
#define TIMER_SPAN 32
#define TIMER_IRQ 2
#define TIMER_ALWAYS_RUN 0
#define TIMER_FIXED_PERIOD 0
#define TIMER_SNAPSHOT 1
#define TIMER_PERIOD 10.0
#define TIMER_PERIOD_UNITS "ms"
#define TIMER_RESET_OUTPUT 0
#define TIMER_TIMEOUT_PULSE_OUTPUT 0
#define TIMER_LOAD_VALUE 999999
#define TIMER_MULT 0.001
#define TIMER_FREQ 100000000
#define ALT_MODULE_CLASS_TIMER altera_avalon_timer

/*
 * UART1 configuration
 *
 */

#define UART1_NAME "/dev/UART1"
#define UART1_TYPE "altera_avalon_uart"
#define UART1_BASE 0x04000040
#define UART1_SPAN 32
#define UART1_IRQ 3
#define UART1_BAUD 115200
#define UART1_DATA_BITS 8
#define UART1_FIXED_BAUD 1
#define UART1_PARITY 'N'
#define UART1_STOP_BITS 1
#define UART1_USE_CTS_RTS 0
#define UART1_USE_EOP_REGISTER 0
#define UART1_SIM_TRUE_BAUD 0
#define UART1_SIM_CHAR_STREAM ""
#define UART1_FREQ 100000000
#define ALT_MODULE_CLASS_UART1 altera_avalon_uart

/*
 * SPI_16 configuration
 *
 */

#define SPI_16_NAME "/dev/SPI_16"
#define SPI_16_TYPE "spi16"
#define SPI_16_BASE 0x04000080
#define SPI_16_SPAN 16
#define ALT_MODULE_CLASS_SPI_16 spi16

/*
 * PIO_IO configuration
 *
 */

#define PIO_IO_NAME "/dev/PIO_IO"
#define PIO_IO_TYPE "altera_avalon_pio"
#define PIO_IO_BASE 0x040000a0
#define PIO_IO_SPAN 16
#define PIO_IO_DO_TEST_BENCH_WIRING 0
#define PIO_IO_DRIVEN_SIM_VALUE 0
#define PIO_IO_HAS_TRI 0
#define PIO_IO_HAS_OUT 1
#define PIO_IO_HAS_IN 1
#define PIO_IO_CAPTURE 0
#define PIO_IO_DATA_WIDTH 16
#define PIO_IO_EDGE_TYPE "NONE"
#define PIO_IO_IRQ_TYPE "NONE"
#define PIO_IO_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_IO_FREQ 100000000
#define ALT_MODULE_CLASS_PIO_IO altera_avalon_pio

/*
 * PIO_TRI configuration
 *
 */

#define PIO_TRI_NAME "/dev/PIO_TRI"
#define PIO_TRI_TYPE "altera_avalon_pio"
#define PIO_TRI_BASE 0x040000b0
#define PIO_TRI_SPAN 16
#define PIO_TRI_DO_TEST_BENCH_WIRING 0
#define PIO_TRI_DRIVEN_SIM_VALUE 0
#define PIO_TRI_HAS_TRI 1
#define PIO_TRI_HAS_OUT 0
#define PIO_TRI_HAS_IN 0
#define PIO_TRI_CAPTURE 0
#define PIO_TRI_DATA_WIDTH 16
#define PIO_TRI_EDGE_TYPE "NONE"
#define PIO_TRI_IRQ_TYPE "NONE"
#define PIO_TRI_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_TRI_FREQ 100000000
#define ALT_MODULE_CLASS_PIO_TRI altera_avalon_pio

/*
 * PIO_STATUS configuration
 *
 */

#define PIO_STATUS_NAME "/dev/PIO_STATUS"
#define PIO_STATUS_TYPE "altera_avalon_pio"
#define PIO_STATUS_BASE 0x040000c0
#define PIO_STATUS_SPAN 16
#define PIO_STATUS_IRQ 4
#define PIO_STATUS_DO_TEST_BENCH_WIRING 0
#define PIO_STATUS_DRIVEN_SIM_VALUE 0
#define PIO_STATUS_HAS_TRI 0
#define PIO_STATUS_HAS_OUT 0
#define PIO_STATUS_HAS_IN 1
#define PIO_STATUS_CAPTURE 1
#define PIO_STATUS_DATA_WIDTH 16
#define PIO_STATUS_EDGE_TYPE "FALLING"
#define PIO_STATUS_IRQ_TYPE "EDGE"
#define PIO_STATUS_BIT_CLEARING_EDGE_REGISTER 0
#define PIO_STATUS_FREQ 100000000
#define ALT_MODULE_CLASS_PIO_STATUS altera_avalon_pio

/*
 * I2C_8 configuration
 *
 */

#define I2C_8_NAME "/dev/I2C_8"
#define I2C_8_TYPE "I2C8"
#define I2C_8_BASE 0x040000e0
#define I2C_8_SPAN 32
#define I2C_8_IRQ 5
#define ALT_MODULE_CLASS_I2C_8 I2C8

/*
 * EXTBRIDGE configuration
 *
 */

#define EXTBRIDGE_NAME "/dev/EXTBRIDGE"
#define EXTBRIDGE_TYPE "pbridge"
#define EXTBRIDGE_BASE 0x10000000
#define EXTBRIDGE_SPAN 67108864
#define ALT_MODULE_CLASS_EXTBRIDGE pbridge

/*
 * custom instruction macros
 *
 */

#define ALT_CI_CONVERTER_N 0x00000000
#define ALT_CI_CONVERTER(A) __builtin_custom_ini(ALT_CI_CONVERTER_N,(A))
#define ALT_CI_VECTOR_N 0x00000001
#define ALT_CI_VECTOR __builtin_custom_in(ALT_CI_VECTOR_N)

/*
 * system library configuration
 *
 */

#define ALT_MAX_FD 5
#define ALT_SYS_CLK TIMER
#define ALT_TIMESTAMP_CLK none

/*
 * Devices associated with code sections.
 *
 */

#define ALT_TEXT_DEVICE       SDRAM
#define ALT_RODATA_DEVICE     SDRAM
#define ALT_RWDATA_DEVICE     SDRAM
#define ALT_EXCEPTIONS_DEVICE SDRAM
#define ALT_RESET_DEVICE      CFI_FLASH


#endif /* __SYSTEM_H_ */

Answer 1

For reconfiguration of an FPGA the Remote System Update IP core from Intel can be used. However, this means adapting the logic of your FPGA.