CODEWITHSUNDEEP
assemblyx86intelcpu-architecture
user997112
user997112

Reputation: 30605

Can atomic instructions straddle cache lines?

Can x86 instructions like LOCK DEC straddle multiple cache lines, or will they seg-fault?

Not asking if they should, just whether its allowed.

(I know certain SSE instructions must be aligned on cache boundaries)

Upvotes: 5

Views: 494

Answers (2)

Leeor
Leeor

Reputation: 19706

It's allowed, but you might get a huge performance degradation as the lock may not be possible to maintain inside the cache, and may downgrade into a full bus-lock (a full system stall, effectively).

See for e.g. - https://software.intel.com/en-us/articles/implementing-scalable-atomic-locks-for-multi-core-intel-em64t-and-ia32-architectures :

In the days of Intel 486 processors, the lock prefix used to assert a lock on the bus along with a large hit in performance. Starting with the Intel Pentium Pro architecture, the bus lock is transformed into a cache lock. A lock will still be asserted on the bus in the most modern architectures if the lock resides in uncacheable memory or if the lock extends beyond a cache line boundary splitting cache lines. Both of these scenarios are unlikely, so most lock prefixes will be transformed into a cache lock which is much less expensive.

It may vary according to the processor spec, but note that one other consideration is that crossing line boundary may also mean crossing a page boundary, which is even harder to maintain (and thus even more likely to downgrade).

Upvotes: 4

Jester
Jester

Reputation: 58762

Yes it's allowed. You could have also just tried it. Or read the instruction set reference:

The integrity of the LOCK prefix is not affected by the alignment of the memory field. Memory locking is observed for arbitrarily misaligned fields.

But see also:

Exceptions

#AC(0) If alignment checking is enabled and an unaligned memory reference is made while the current privilege level is 3.

Note that alignment checking is not usually enabled.

Upvotes: 4

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