Swap elements in an array - VHDL

Question

I have a piece of code in VHDL:

I want to swap the signalIn(0) and signalIn(1) values.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity SwapFP is
port(clockIn:in std_logic);
end SwapFP;

architecture Behavioral of SwapFP is    

signal tempOne,tempTwo,a1,a2 : STD_LOGIC_VECTOR(31 DOWNTO 0);  

signal state : integer range 0 to 7 := 0;

begin 

  process(clockIn) is
  type floatingPointArray is array(1 downto 0) of std_logic_vector(31 downto 0);
  variable signalIn : floatingPointArray;

  begin

  signalIn(0) := X"3D52CEF8";
  signalIn(1) := X"3FBC9F1A";

  if rising_edge(clockIn) then

    case state is

    when 0 =>
        tempOne <= signalIn(0);
        tempTwo <= signalIn(1);
        state <= 1;
    when 1 =>
        signalIn(1) := tempOne;
        signalIn(0) := tempTwo;
        state <= 2;

    when 2 =>
        a1 <= signalIn(0);
        a2 <= signalIn(1);
        state <= 3;
    when others =>

    end case;

  end if;  

  end process;

end Behavioral;

In a1 and a2 signals, I am getting the original values X"3D52CEF8" and X"3FBC9F1A" respectively. Means that swapping is not happening. Why is it so?

Answer 1

Your variable assignments to signalIn at the top of the process happen every time the process runs. When state is 2, the values you assigned to signalIn when state equaled 1 are overwritten by this initial assignment.

You can much more easily swap two items like this:

process (clk)
begin
  if (rising_edge(clk)) then
    signalIn(0) <= signalIn(1);
    signalIn(1) <= signalIn(0);
  end if;
end process;

This works because the signal assignments using <= do not take place immediately, rather they are scheduled to take place after the process has run.