CODEWITHSUNDEEP
structbit-manipulationverilogsystem-verilog
John M
John M

Reputation: 1496

Bitwise-or all fields in Verilog struct

Let's say that I have an array of buses, each one carrying a struct like so:

typedef struct packed {
    logic [31:0] piano_concerto_in_d_minor;
    logic [31:0] piano_concerto_in_c_minor;
    logic [7:0]  nationality;
} rachmaninov_t;

//.........
module russian_composers(/* input/output busses go here */);
    rachmaninov_t [2] rachs;
    rachmaninov_t     output;
    assign rachs[0] = {32'haaaa5555, 32'h10001000, 8'h33};
    assign rachs[1] = {32'h5555aaaa, 32'h80008000, 8'h44};

And I want to bitwise or them together, I would do the following:

    assign output = rachs[0] | rachs[1];
    //value of output is {32'hffffffff, 32'h90009000, 8'h77}
endmodule

Now, what would I do if I had a parameterized number of rachmaninov_t structs and I wanted to bitwise-or all of them together like above? I've already tried

assign output = |rachs;

and it doesn't work (which isn't too surprising).

Could I get a generate block to do this?

Upvotes: 1

Views: 2342

Answers (2)

dave_59
dave_59

Reputation: 42673

Perhaps you want the bitwise-or reduction method described in 7.12.3 Array reduction methods

assign output = rachs.or();

Upvotes: 3

Unn
Unn

Reputation: 5098

While you can use a generate for this, you can also just use a plain old for loop inside your combinational logic to do this:

parameter NUM = 4; // The number of structs you need to or together
...
int i;

always_comb begin 
  output = '0;
  for (i = 0; i < NUM; i = i + 1) begin
    output |= rachs[i];
  end
end

Just realize this will synthesize into a chain of or; which hopefully the synthesis tool might reform into a larger or or a tree, but Im not sure if it would.

Upvotes: 3

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