CODEWITHSUNDEEP
hardwareendiannesscpu-architectureamba
JeffB
JeffB

Reputation: 406

How are bytes mapped to AXI4 bus on a little endian system

If a program running on a little endian processor writes the value 0xaabbccdd uncached to address 0, and the processor uses a 32-bit wide AXI4 bus, are bits 31-24 of WDATA 0xaa or 0xdd?

AXI does not expose byte addressable memory--it can only read or write a full data bus width (32 bits in this case). The question is how it maps addresses of byte values to data bus bits.

Section A3.4.3 of the AXI spec (rev E) discusses "byte invariant" endianness, but doesn't seem to explain the order of bytes on the data bus.

Upvotes: 4

Views: 4166

Answers (1)

Juglans
Juglans

Reputation: 31

If a little endian processor writes the value 0xaabbccdd uncached to address 0 via a 32-bit wide AXI4 bus, are bits 31-24 of WDATA 0xaa or 0xdd?

31-24 bits of WDATA are 0xAA independent of processor endianness. But the order of bytes in memory is determined by the endianness. See this answer for explanation of byte-invariant endianness.

Upvotes: 2

Related Questions