CODEWITHSUNDEEP
vhdlclockxilinxmodelsim
arandomuser
arandomuser

Reputation: 571

Passing clock between entities

my doubt is how to pass a clock between two entities that are at the same hierarchical level in VHDL. What I have is an entity "wrapper" in which there are instantiated two components "comp_1" and "comp_2". comp_1 has an output port (let's say "clk_out") that is its clock and that must be also the clock for comp_2. Now, if I use a signal in "wrapper" to pass the clock from comp_1 to comp_2, this cause a functional error in simulation (at least with Modelsim), because the two designs are considered not synchronous (right?). Can this cause an error also in synthesis (with Xilinx)? How can I avoid the problem without changing all the structure?

architecture bhv of my_wrap is
    signal tmp_clk : std_logic;
begin

comp_1_i : comp_1
    port map(out_clk => tmp_clk,  
             ...
    );

compo_2_i : comp_2
    port map(in_clk => tmp_clk, 
             ...
    );

In this case, in simulation there is the delta cycle problem in the signals between the two components. Can this problem also affect the implemented design on FPGA?

Upvotes: 1

Views: 1103

Answers (2)

Rasmus B. Sorensen
Rasmus B. Sorensen

Reputation: 76

As Morten also pointed out some source code could help making your question more precise.

There is nothing wrong in connecting the clock out signal from one component to the clock in signal of another component. What might be a problem in your case is the way you generate the clock signal. Depending on your use case you have different options. If your target is an FPGA you should use a clock generator IP form the given vendor.

Upvotes: 1

Morten Zilmer
Morten Zilmer

Reputation: 15924

It sounds like you may have a delta cycle delay on the clock, which is a feature in VHDL, but it may appear as if clock and data is out of sync.

This only shows in simulation, but is general VHDL thus not ModelSim specific. After synthesis (in hardware) the internal delay gives similar behavior. Note that ModelSim has a feature ("Expanded Time Delta Mode") to show delta delays.

Without code, I guess that the generated clock in comp_1 is also used for output generation, besides being output on clk_out. Depending on the implementation, it may result in a delta cycle delay difference between clock and data, which is may appear as not synchronous, but it is actually a delta cycle issue.

A possible fix is to output the generated clock from comp_1 without using it, and then making an additional clk_in input on comp_1, similar to the clk_in on comp_2, and then use that clock internally in comp_1. The clock use will then be similar on comp_1 and comp_2, removing the issue with delta delays on clock.

Upvotes: 3

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