Reputation: 81
I was going through the LDD3 when I stumbled across the below statement.
"Timer interrupts are generated by the system's timing hardware at regular intervals; this interval is programmed at boot time by the kernel according to the value of HZ, which is an architecture-dependent value defined in or a subplatform file included by it."
What my thought was that the timer interrupts had to solely to do with the processor speed and its a non-configurable entity. Now this statement confuses me. Can somebody please explain it to me.
Upvotes: 1
Views: 705
Reputation: 191
On core timer hardware is generally a digital frequency divider programmed to take input frequency as CPU clock frequency and output is a fraction of input frequency. CPU clock frequency is not programmable but the timer hardware i.e frequency divider is programmed on the basis of value of HZ to interrupt the core periodically. [1]: https://en.wikipedia.org/wiki/Frequency_divider
Upvotes: 1