CODEWITHSUNDEEP
functionif-statementcasevhdl
Bao Thai
Bao Thai

Reputation: 553

Declaring multiple cases with the same function?

I am a beginner to VHDL, started coding for a class I am in. I am working on a digital-alarm-bike lock, I am trying to find an efficient way to call this code, but I am currently getting a syntax error.

PROCESS (Clk, H)
BEGIN
    CASE current_state IS
        WHEN s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s63=>
            IF H = "0" THEN
                current_state <= s0;
            END If;
        WHEN s12,s13,s14,s15,s16,s17,s18,s19,s20,s21,s22,s23,s24,s25,s26,s27,s28,s29,s30,s31,s32,s33,s34,s35,s36,s37,s38,s39,s40,s41,s42,s43,s44,s45,s46,s47,s48,s49,s50,s51,s52,s53,s54,s55,s56,s57,s58,s59,s60,s61,s62=>
            IF H = "0" THEN
                current_state <= s52;
            Elsif (rising_edge(Clk) THEN
                current_state <= next_state;
            END IF;
     END CASE
END PROCESS;

Basically, those are state types, and I want to basically call all those states, and check them for the value of H, and certain condition will be called. However, I am getting this error:

ERROR:HDLParsers:164 - "(Directory///)" Line 50. parse error, unexpected COMMA, expecting PIPE or ROW

I can't use a comma, but does any experienced VHDL code know how to work around this so we do not have to explicitly repeat the code for each s-state?

Upvotes: 0

Views: 70

Answers (2)

user1818839
user1818839

Reputation:

If you'd looked a little harder, you could have found

WHEN s0 to s11|s63 => 
   ...
WHEN s12 to s62 =>
   ...

Upvotes: 3

Bao Thai
Bao Thai

Reputation: 553

I found the solution for my own question hahaha.

There is a "pipe" symbol that allows for this operation.

PROCESS (Clk, H)
BEGIN
    CASE current_state IS
        WHEN s0|s1|s2|s3|s4|s5|s6|s7|s8|s9|s10|s11|s63=>
            IF H = '0' THEN
                current_state <= s0;
            END If;
        WHEN s12|s13|s14|s15|s16|s17|s18|s19|s20|s21|s22|s23|s24|s25|s26|s27|s28|s29|s30|s31|s32|s33|s34|s35|s36|s37|s38|s39|s40|s41|s42|s43|s44|s45|s46|s47|s48|s49|s50|s51|s52|s53|s54|s55|s56|s57|s58|s59|s60|s61|s62=>
            IF H = '0' THEN
                current_state <= s52;
            Elsif (rising_edge(Clk)) THEN
                current_state <= next_state;
            END IF;
     END CASE;
END PROCESS;

Upvotes: 1

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