CODEWITHSUNDEEP
verilog
MTMD
MTMD

Reputation: 1232

What is the best way to give name to different cases in Verilog?

I was wondering if someone can tell me what is the best way to give name to different states in Verilog? For example instead of the following case

case (a)
  1'b0 : statement1;
  1'b1 : statement2;
  1'bx : statement3;
  1'bz : statement4;
endcase

It is much better to have a piece of code with this format

case (a)
  Load : statement1;
  Store : statement2;
  Check : statement3;
  Reset : statement4;
endcase

Upvotes: 1

Views: 1029

Answers (2)

Morgan
Morgan

Reputation: 20514

If not wanting to use enums then localparams are also a good way of using mnemonics for your states.

localparam LOAD  = 1'b0;
localparam STORE = 1'b1;
localparam CHECK = 1'bx;
localparam RESET = 1'bz;

always @* begin
  case (a)
    LOAD : statement1;
    STORE : statement2;
    CHECK : statement3;
    RESET : statement4;
  endcase
end

Most languages use upper case to denote constants, it is also good practice to do this in Verilog with localparams and parameters.

Upvotes: 2

sharvil111
sharvil111

Reputation: 4381

An enum of logic type can help you out. For example, the state variables like IDLE,BUSY etc. of state machine can only have the all the states defined and can be displayed using the state name, that is enums.

Enums can be defined as follows:

enum logic {Load,Store,Check,Reset} a;

You can explicitly assign values to enum as follows:

enum logic {Load='0,Store='1,Check='x,Reset='z} a;

Also, you have built-in methods like first, last, name etc. to perform operations on enums.

Here is an exact code what I am trying to explain:

module top();
  enum logic {Load='0,Store='1,Check='x,Reset='z} a;
  initial
    begin
      case (a)
        Load : $display("1");
        Store :  $display("2");
        Check :  $display("3");
        Reset :  $display("4");
      endcase
    end 
endmodule

For more information, refer to Enumerations link.

Upvotes: 1

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