CODEWITHSUNDEEP
vhdl
Daniel Hall
Daniel Hall

Reputation: 854

VHDL test bench, configuration unit

I have been trying to use a test bench with a configuration unit. I have the following code:

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY AND_2 IS
PORT (
        a,b :   IN      std_logic;
        x       :   OUT std_logic
        );
END ENTITY AND_2;

ARCHITECTURE EX_1 OF AND_2 IS
BEGIN
x <= a and b;
END ARCHITECTURE EX_1;

ARCHITECTURE EX_2 OF AND_2 IS
SIGNAL ab   :   std_logic_vector(1 DOWNTO 0);
BEGIN
ab <= (a & b);
WITH ab SELECT
    x <= '1' WHEN "11",
          '0' WHEN OTHERS;
END ARCHITECTURE EX_2;

LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

ENTITY TEST_AND_2 IS
END ENTITY TEST_AND_2;

ARCHITECTURE IO OF TEST_AND_2 IS
SIGNAL a, b, x  :   std_logic;
BEGIN
G1      :   ENTITY work.AND_2(EX_1) PORT MAP ( a => a, b => b, x => x);
a <= '0', '1' AFTER 100 NS;
b <= '0', '1' AFTER 200 NS;
END ARCHITECTURE IO;

CONFIGURATION TESTER1 OF TEST_AND_2 IS
FOR IO
    FOR G1 : AND_2
        USE ENTITY work.AND_2(EX_1);
    END FOR;
END FOR;
END CONFIGURATION TESTER1;

When I compile I kindly receive back the following message:

Error (10482): VHDL error at AND_2.vhd(48): object "AND_2" is used but not declared

The book I am reading from is not to clear in the use of test bench or the configuration unit. Can some one point out the mistake. However obvious it may be. Many Thanks D

Upvotes: 2

Views: 1155

Answers (1)

scary_jeff
scary_jeff

Reputation: 4384

You cannot use configurations in this way if you are using direct instantiation for your entity. Where you have:

G1 : ENTITY work.AND_2(EX_1) PORT MAP ( a => a, b => b, x => x);

This is direct instantiation, which in general saves typing and duplicated code, but will not allow the architecture to be specified by a configuration. To use configurations, in your declarative region (where the signals are defined), declare a component for your AND_2:

COMPONENT AND_2 IS
PORT (
    a,b :   IN      std_logic;
    x       :   OUT std_logic
    );
END COMPONENT;

Then instantiate the AND_2 like this:

G1 : AND_2 PORT MAP ( a => a, b => b, x => x);

Your configuration statement is correct, you should be up and running with these two changes.

Upvotes: 3

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