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if-statementvhdl
Yvonne Sun
Yvonne Sun

Reputation: 31

VHDL how to have multiple conditions in if statement

I'm trying to do an if statement that checks if bet_target is one of many numbers, the code looks something like this: 

bet_target : in unsigned(5 downto 0);

if (bet_target = 1 or bet_target = 2 or bet_target = 3) then
            --do stuff  
end if;

The bet target is any number from 0 to 36 in binary from 6 switches. Is there a more compressed way for writing a statement as such?

Thanks

Upvotes: 3

Views: 25935

Answers (1)

user1155120
user1155120

Reputation:

If you're using the IEEE package numeric_std you can use comparisons as in 

if bet_target >= 0 and bet_target <= 36 then
    ...

Note that unsigned expects natural range integer values as operands for relational operators.

(Also note the superfluous parentheses have not been included - they are permitted).

These relational operators return boolean values and the and in the middle would be a boolean logical operator.

The place to look for how and why is in the IEEE numeric_std package declarations and IEEE Std 1076-2008 9.2 Operators.

And realizing that an unsigned is going to have a binary equivalent of a natural number you could express this with a single condition:

if bet_target <= 36 then
    -- do something

end if;

Upvotes: 3

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