CODEWITHSUNDEEP
computer-sciencecpu-architecturerisc
YaserM
YaserM

Reputation: 187

CISC and RISC architectures

I read a lot about the difference between CISC and RISC architectures from different sources. One of the things that seemed to be agreed upon is that CISC is always used with Von Neumann whereas RISC is used with Harvard architecture. But I couldn't quite grasp the reason behind this classification.

Upvotes: 2

Views: 7529

Answers (2)

jorgbrown
jorgbrown

Reputation: 2051

Von Neumann vs Harvard isn't a clearcut difference. Obviously a chip with separate memory busses for instruction and data is Harvard architecture. But the performance benefit of separate busses is greatly reduced when good caches are added.

If you take such a chip and add good caches, and then switch back to a single memory bus, where an extra pin indicates whether the memory fetch is for instruction or for data, you're still really talking about a Harvard architecture - and from a programming perspective, you can't tell that such a change has happened.

I think probably the biggest difference is that on a true Von Neumann CPU, you can write to the instruction memory, and then immediately execute the instructions you wrote. On an 8086, for example, you can write to the instruction immediately after the write instruction! Whereas on a Harvard CPU, even one with a unified memory bus, you'd have to follow the write with an instruction to force that write out to actual memory, possibly an instruction to prevent out-of-order execution, and then an instruction to flush the instruction cache at that location. This process can take several hundred cycles - and it's necessary because the architecture of the chip assumes that instruction and data memory don't interact.

This change can even take place within the same CPU family. The original cache-less 68000 is certainly a CISC CPU, but if you write to the instruction stream, you have to beware of the instruction prefetch, and potentially add a NOP after your write to memory. Later variations of the 680x0 family, however, became more and more Harvard-like. The external memory bus may have remained unified, but instruction and data caches were separate, for example.

Upvotes: 1

Rishit Sanmukhani
Rishit Sanmukhani

Reputation: 2269

There is no relations between Instruction Set (RISC and CISC) with architecture of the processor (Harvard Architecture and Von Neumann Architecture). Both instruction set can be used with any of the architecture.

Older ARM architecture used Von Neumann Architecture with RISC, and later with ARM9 they shifted to Harvard Architecture with RISC. Latest ARM processor uses much more advanced hybrid architecture.

Upvotes: 12

Related Questions