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vhdldoxygen
Rafael Catrou
Rafael Catrou

Reputation: 185

Doxygen for VHDL : how to ignore portion of code in a file

I use doxygen for VHDL files using the option "OPTIMIZE_OUTPUT_VHDL = YES".

I intend to filter warnings '... is undocumented' for declaration of signals, variables, types, component and attributes (id est: almost everything between ARCHITECTURE and BEGIN).

The command @cond seems to be the appropriate answer but I didn't manage to make it work in the VHDL context.

--! @cond
signal my_signal : std_logic;
--! @endcond

With this code, doxygen outputs the following messages

warning: Found unknown command '\cond'
warning: Found unknow command '\endcond'

What is the best way to achieve warnings filtering in VHDL context?

EDIT: Doxygen version 1.8.11

Upvotes: 3

Views: 1083

Answers (2)

Rafael Catrou
Rafael Catrou

Reputation: 185

The root of the issue is that the tag @cond only work when it is strictly at the beginning of the line. On contrary to the other doxygen comments, it does not work when indented.

example that works

--! @cond
  signal my_signal_filtered : std_logic;
--! @endcond

Note: between ARCHITECTURE and BEGIN, declarations use to be indented one time. That's why I get trapped :)


example that DOES NOT work because of the 2 spaces indentation:

  --! @cond
  signal my_signal : std_logic;
  --! @endcond

Upvotes: 1

dieli
dieli

Reputation: 179

I put before my constants/after:

  --! @cond CONSTANTS
  --! @endcond

and 

  --! @cond SIGNALS
  --! @endcond

before/after signals, e.g. give the condition a name. And in my doxygen.conf the enabled sections is empty:

ENABLED_SECTIONS       =

Works for me in Doxygen 1.8.6

EDIT: wording was confusing

Upvotes: 0

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