timing analysis report for ASIC synthesis

Question

I am having some problems in getting a pre place&routing timing analysis report for ASIC synthesis

to get timing we should use ABC in the flowing steps:

1-­strash­-Transforms the current network into an AIG(graph with two logic gate “AND/OR”)

[*Structural hashing is a purely combinational transformation]

2­-scorr­- I did not know what does this command do. so the first question is: what does this command do?

2.1­ when I am using this command I get some errors :

if I using Combinational circuits like

module combinational(a, b, sel, out);

input a, b;

input sel;

output out;

reg out;

always @ (a or b or sel)

begin

if (sel) out = a;

else out = b;

end

endmodule

iget error ABC: Error: The network is combinational (run "fraig" or "fraig_sweep").

From yosys the synth.log output :

 2.1.1. Executing ABC.
Running ABC command: <yosys-exe-dir>/berkeley-abc -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_lib -w /usr/local/share/qflow/tech/osu035/osu035_stdcells.lib 
ABC: Parsing finished successfully.  Parsing time =     0.00 sec
ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFFNEGX1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFFPOSX1".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFFSR".
ABC: Scl_LibertyReadGenlib() skipped sequential cell "LATCH".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "PADINOUT".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "TBUFX1".
ABC: Scl_LibertyReadGenlib() skipped three-state cell "TBUFX2".
ABC: Scl_LibertyReadGenlib() skipped cell "PADFC" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "PADNC" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "PADVDD" without logic function.
ABC: Scl_LibertyReadGenlib() skipped cell "PADGND" without logic function.
ABC: Library "osu035_stdcells" from "/usr/local/share/qflow/tech/osu035/osu035_stdcells.lib" has 28 cells (11 skipped: 4 seq; 3 tri-state; 4 no func).  Time =     0.01 sec
ABC: Memory =    0.38 MB. Time =     0.01 sec
ABC: Warning: Detected 2 multi-output gates (for example, "FAX1").
ABC: + strash 
ABC: + scorr 
ABC: Error: The network is combinational (run "fraig" or "fraig_sweep").
ABC: + ifraig 
ABC: + retime 
ABC: + strash 
ABC: + dch -f 
ABC: + map 
ABC: + write_blif <abc-temp-dir>/output.blif 

12.1.2. Re-integrating ABC results.
ABC RESULTS:             INVX1 cells:        1
ABC RESULTS:           NAND2X1 cells:        3
ABC RESULTS:        internal signals:        0
ABC RESULTS:           input signals:        3
ABC RESULTS:          output signals:        1
Removing temp directory.

if I give sequential like

module  sequential(a, b, sel,
clk, out);
input a, b;
input sel, clk;
output out;
reg out;
always @ (posedge clk)
begin
if (sel) out <= a;
else out <= b;
end
endmodule

also we have the same error

for this module:


module blocking(in, clk, out);
input in, clk;
output out;
reg q1, q2, out;
always @ (posedge clk)
begin
q1 = in;
q2 = q1;
out = q2;
end
endmodule

iget

12. Executing ABC pass (technology mapping using ABC).
12.1. Extracting gate netlist of module `\blocking' to `<abc­temp­dir>/input.blif'..

Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Don't call ABC as there is nothing to map.
Removing temp directory.

3-­from the error we know that we should run "fraig" or "fraig_sweep"

3.1­ fraig-

Transforms the current network into a functionally­ reduced AIG

3.2­ fraig_sweep ­Detects functionally equivalent nodes in a logic network. Unlike fraig this command preserves the network structure and only merges the functionally equivalent nodes

4­-ifraig­ i did not know what it do also what this command do?

5­-In retime /map commands what you mean in {d}

in:

**

> for ­liberty with ­constr:  strash; scorr; ifraig; retime {D};
> strash; dch -­f; map {D}; buffer;
upsize {D}; dnsize {D}; stime ­p

**

In dch -­f we should give it a script file**?** And what dch command should do?

And why it failed to map?

**

*in one word how do we get and print a pre place&routing timing analysis report for ASIC?

and does it work for all circuits parallel,sequential,...or it does not work in all verilog files?

And I want to know what should every step in ABC do?

**

Answer 1

According to your question you have used the following module:

module blocking(in, clk, out);
input in, clk;
output out;
reg q1, q2, out;
always @ (posedge clk)
begin
q1 = in;
q2 = q1;
out = q2;
end
endmodule

Besides the fact that this module introduces a simulation race condition (see this paper, your code is pretty much identical to "Example 5 - Bad blocking-assignment sequential coding style #1"), this module describes just a single D-type flip-flop (generated with yosys -p 'proc; opt; show):

The default behavior for the Yosys abc command is to only consider the logic portion of the design (no retiming is performed unless the abc command is called with the -dff option, see help abc in Yosys).

Because there is no logic at all in this module, and the abc command acts on the logic portion of the module, you naturally get:

Extracted 0 gates and 0 wires to a netlist network with 0 inputs and 0 outputs.
Don't call ABC as there is nothing to map.
Removing temp directory.

Regarding the message Error: The network is combinational (run "fraig" or "fraig_sweep").: This is simply an error generated by scorr when handling an input that is purely combinational. (See scorr -h in yosys-abc for a description of what scorr does. It only makes sense for sequential input networks and thus it is a no-op when abc is no called with -dff.) Abc simply continues with the next command, as you can see in the output you have quoted. Nothing is wrong here.

in one word how do we get and print a pre place&routing timing analysis report for ASIC?

By calling abc with a delay target -D <picoseconds> and a constr file -constr <file> while mapping to an ASIC library with -liberty <file>.

or it does not work in all verilog files?

as you have seen, it does not work on circuits that contain no logic at all, because then there is nothing to map and analyse.