Synopsys Design Compiler and PrimeTime timing analysis report remain same

Question

I had done the timing analysis of a counter in both Synopsys Design Compiler and PrimeTime, but got the same output! Any problem ?

Then how PrimeTime timing analysis will become more accurate than DC?

Design file used is counter.v and is given below.

module counter ( out, clk, reset ) ;

   input        clk, reset;
   output [3:0] out;

   reg [3:0]    out;

   wire [3:0]   next;

   // This statement implements reset and increment
   assign       next = reset ? 4'b0 : (out + 4'b1);

   // This implements the flip-flops
   always @ ( posedge clk ) begin
      out <= #1 next;
   end


endmodule // counter

Design compiler output is generated by giving input as counter.v , and clock period of 2.The Design Compiler output is shown below.

write_sdf ${name}.sdf
Information: Annotated 'cell' delays are assumed to include load delay. (UID-282)
Information: Writing timing information to file '/home/student/labs/jithin_prjct/jith/count.sdf'. (WT-3)
Information: Updating design information... (UID-85)
1
create_clock clk -period 2
1
report_timing
Information: Updating graph... (UID-83)
Information: Updating design information... (UID-85)

****************************************
Report : timing
        -path full
        -delay max
        -max_paths 1
Design : count
Version: E-2010.12-SP2
Date   : Fri Mar 20 22:08:55 2015
****************************************

Operating Conditions: TYPICAL   Library: saed90nm_typ
Wire Load Model Mode: enclosed

  Startpoint: out_reg[0] (rising edge-triggered flip-flop clocked by clk)
  Endpoint: out_reg[3] (rising edge-triggered flip-flop clocked by clk)
  Path Group: clk
  Path Type: max

  Des/Clust/Port     Wire Load Model       Library
  ------------------------------------------------
  count              ForQA                 saed90nm_typ

  Point                                    Incr       Path
  -----------------------------------------------------------
  clock clk (rise edge)                    0.00       0.00
  clock network delay (ideal)              0.00       0.00
  out_reg[0]/CLK (DFFX1)                   0.00       0.00 r
  out_reg[0]/Q (DFFX1)                     0.18       0.18 f
  U25/QN (NOR2X0)                          0.11       0.29 r
  U21/Q (AO21X1)                           0.12       0.41 r
  U15/Q (AO21X1)                           0.10       0.51 r
  U14/Q (MUX21X1)                          0.12       0.63 r
  out_reg[3]/D (DFFX1)                     0.04       0.67 r
  data arrival time                                   0.67

  clock clk (rise edge)                    2.00       2.00
  clock network delay (ideal)              0.00       2.00
  out_reg[3]/CLK (DFFX1)                   0.00       2.00 r
  library setup time                      -0.07       1.93
  data required time                                  1.93
  -----------------------------------------------------------
  data required time                                  1.93
  data arrival time                                  -0.67
  -----------------------------------------------------------
  slack (MET)                                         1.26

PrimeTime output is generated by giving input as netlist file of counter , SDF file of counter (both generated from Design Compiler) and clock period of 2. The PrimeTime output is shown below.

report_timing
****************************************
Report : timing
    -path_type full
    -delay_type max
    -max_paths 1
Design : count
Version: E-2010.12-SP1
Date   : Fri Mar 20 22:08:14 2015
****************************************


  Startpoint: out_reg[0] (rising edge-triggered flip-flop clocked by clk)
  Endpoint: out_reg[3] (rising edge-triggered flip-flop clocked by clk)
  Path Group: clk
  Path Type: max

  Point                                    Incr       Path
  ---------------------------------------------------------------
  clock clk (rise edge)                    0.00       0.00
  clock network delay (ideal)              0.00       0.00
  out_reg[0]/CLK (DFFX1)                   0.00       0.00 r
  out_reg[0]/Q (DFFX1)                     0.18 *     0.18 f
  U25/QN (NOR2X0)                          0.11 *     0.29 r
  U21/Q (AO21X1)                           0.12 *     0.41 r
  U15/Q (AO21X1)                           0.10 *     0.51 r
  U14/Q (MUX21X1)                          0.12 *     0.63 r
  out_reg[3]/D (DFFX1)                     0.04 *     0.67 r
  data arrival time                                   0.67

  clock clk (rise edge)                    2.00       2.00
  clock network delay (ideal)              0.00       2.00
  out_reg[3]/CLK (DFFX1)                              2.00 r
  library setup time                      -0.07 *     1.93
  data required time                                  1.93
  ---------------------------------------------------------------
  data required time                                  1.93
  data arrival time                                  -0.67
  ---------------------------------------------------------------
  slack (MET)                                         1.26

Answer 1

You provide PrimeTime with netlist and SDF(Standard Delay Format, the timing delay info), and SDF is generated by Design Compiler. In your case, PrimeTime will not calculate cell/net delay by itself because you already provide SDF to PrimeTime. So PrimeTime timing is as same as Design Compiler.

In ASIC design flow, PrimeTime is used pre-place&route also post-place&route. In pre-place&route stage, we use PrimeTime to analyze the timing to confirm the timing goal is achievable in place&route. In post-place&route stage, we use PrimeTime to signoff the post-layout timing and the input data is netlist and extracted RC.

Anyway, it's not common to provide PrimeTime with SDF. PrimeTime has accurate delay calculator so it's not necessary to input SDF. Instead we use PrimeTime to generate SDF for other tools to analyze timing.

Answer 2

You will get different results only when the analysis is performed over the post-layout Netlist. With pre-layout Netlist, you're feeding the tool with the same data from .lib files to perform timing analysis, either in Design Compiler or PrimeTime. Post-layout netlist includes clock tree synthesis, and that's when you get to use PrimeTime. Furthermore, notice you can only analyse setup requirements, and no hold requirements while in pre-layout netlist.