CODEWITHSUNDEEP
verilogtimedelay
Nirmal Sheet
Nirmal Sheet

Reputation: 103

How to include time delay in synthesized verilog?

I am trying to write a synthesizable code in verilog, in which I require to include a time delay of few seconds. I have done the simulation using #delay, but this is not acceptable by synthesizer.

In the process of synthesizing a FSM, which change its states not based on some condition but after few seconds of time delay, I want the above time delay method. FSM has to switch states say from state_1 to state_2 after 4 seconds and state_2 to state_3 after 2 seconds and so on.

Upvotes: 3

Views: 9902

Answers (3)

Ibrahima Barry
Ibrahima Barry

Reputation: 51

If you have a clock of some frequency you can use a repeat statement. If you have a clock with a period of 1.25ns and you want to model a delay of 100ns. Then you need 1.25 * 100 = 125 cycles of your clock. You can do this then:

repeat (125) begin
    @(posedge clk);
end
// do stuff now

Upvotes: 1

Reddy
Reddy

Reputation: 98

For switching the states after a time delay,I hope this code helps.

current_state=state_1;
for(i=0;i<=timedelay*freq;i=i+1)
@posedge;
current_state=state_2;

Upvotes: 2

Peter de Rivaz
Peter de Rivaz

Reputation: 33509

If you know your clock frequency is x Hz, and you want to wait y seconds, then simply use a counter and wait until you reach the number x*y.

e.g. for a clock of 1kHz and a delay of 3 seconds this code will trigger do_something after the time delay.

`define CLOCK_FREQ 1000
`define TIME_DELAY 3

reg [31:0] count=0;

assign do_something = (count==`CLOCK_FREQ*`TIME_DELAY);

always @(posedge clk)
begin
   count <= count + 1'b1;
end

Upvotes: 7

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