CODEWITHSUNDEEP
delayverilog
Awais Hussain
Awais Hussain

Reputation: 442

how to generate delay on xilinx spartan 6 board?

I am learning Verilog HDL. And now, I am trying to run a program on Digilent Atlys Spartan 6 xc6slx45.
I am implementing this counter on the board.

module counter_s2( output reg [7:0] count);

initial begin
  count=0;
  repeat(127) begin
    #10000000 count=count+1;
  end
end

endmodule

When I run this code on the board, I get final input of 1111111. There is no delay coming on the board. I want to produce a delay of, lets say 1 second, to see the output. Thanks!

P.S: I am new to Verilog.

Upvotes: 0

Views: 923

Answers (1)

Morgan
Morgan

Reputation: 20554

What you have created is fine for a testbench component and will work in simulation, but certain parts of it are not synthesisable.

In particular initial can only be used on fpgas to set initial values, it can not change over time with in this block, it could be updated in a separate block. NB: this is the only time when two blocks can set the same reg.

#delay values are ignored by synthesis. arbitrary asynchronous timing control can not be implemented reliably and so is not part of the synthesis tools.

To develop Verilog counters a clock is normally used, this meant he counter value will be held in a flip-flop. For the count to be observable you will need a clock slow enough.

The following counter will overflow and keep counting continuously 

module counter_s2( 
  input            clk,
  output reg [7:0] count
);

initial begin
  count= 'b0;
end

always @(posedge clk) begin
 count <= count + 1 ;
end

endmodule

If it is for ASIC then you should be using resets instead of relying on initial.

module counter_s2( 
  input            clk,
  input            rst_n, //Active Low reset
  output reg [7:0] count
);

always @(posedge clk or negedge rst_n) begin
  if (~rst_n) begin
    count <= 'b0;
  end
  else begin
    count <= count + 1 ;
  end
end

endmodule

Upvotes: 1

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