CODEWITHSUNDEEP
verilog
NickCash99
NickCash99

Reputation: 31

Why don't delays synthesize in Verilog?

I am trying to understand what goes on behind the scenes in Verilog. Why don't delays synthesize in Verilog? Is there something going on with the actual synthesis of the gates that prevent this?

Upvotes: 2

Views: 587

Answers (3)

Hugo Cavalcante
Hugo Cavalcante

Reputation: 89

Use the compiler directive

/* synthesis keep */

It will preserve sequences of logic gates with trivial responses, such as buffers or inverters, which are used to produce delay.

Verilog keep uses

Upvotes: 0

Oldfart
Oldfart

Reputation: 6259

Why don't delays synthesize

Because delays are notorious difficult to implement.

To start with: a delay cell has a huge range. Depending on voltage and temperature and even more: process,the actual delay can vary by a factor 2 or more. It is very simple to specify a delay of 2ns in Verilog, it is very, very difficult to make and nowadays (almost?) impossible to implement in silicon without some reference clock. I can imagine that if somebody would make delays synthesizable, you have to specify them as (min,typ,max) delays.

Places where you find delays are in I/O cells, high speed ser-des ports, DDR interface etc. Those have a calibration or some other learning circuit to control the delay. Even then you will find that regular re-calibration is requires to compensate drift due to temperature and voltage.

If you have an FPGA it gets even more difficult. As you can see in the timing, a great deal of the delay nowadays is in the nets. Thus if you want a delay of 2ns you have to subtract the delay to and from the delay cell. That again only works if the delay drives only one gate. If you need to drive multiple end-points the delay to each will differ, unless you are lucky enough that each path has the same delay (Length, resistance and capacitance.)

On top of that you need a programmable delay cell. I have no idea how big those would be, what range (what about a 2 second delay ?) or how many you need.

Bottom line: the ASIC/FPGA community has found that delays cause more trouble then they solve. It is one of those "short-cuts" which tend to prove in most cases to be a "dead-end".

Upvotes: 6

dave_59
dave_59

Reputation: 42698

Because RTL synthesis tools have chosen to remain in the digital domain of functionality. Synthesizing delays require knowledge of analog characteristics and implementation details.

The way Synthesis tools work is they first take the RTL description and generate sets of Boolean equations. There is no way to represent a delay in Boolean algebra.

Upvotes: 5

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