CODEWITHSUNDEEP
delayverilogfpga
his_dudeness
his_dudeness

Reputation: 43

How to fix the delay error in my Verilog code?

I want to use a delay with # symbol, but the code gives error because of it. If I remove it, then the program works. Here is the code:

module b5(
input wire switch,
output wire led
);

 #100 assign led = switch;

endmodule

Upvotes: 1

Views: 300

Answers (1)

Greg
Greg

Reputation: 19104

The delay is in the wrong location. it should be assign #100 led = switch;

FYI: # delays only work in simulations. If you plan on synthesizing (such as running on FPGA), then you cannot use # delay. Use a clocked pipe-line instead.

Upvotes: 2

Related Questions