CODEWITHSUNDEEP
verilogfpga
Bruno
Bruno

Reputation: 458

What is wrong in this verilog code?

I'm studying verilog and trying to apply the concepts in my fpga. It supossed to work in this way : When Switch 1 is on, all red leds turn on. When Switch 2 is on, all green leds turn on. When Switch 3 is on, all leds turn on. The problem is when I put it in my fpga switch . Could someone tell me why? Here's my code :

module LED (

    input CLOCK_50,
    input [17:0] SW,
    output reg [17:0] LEDR,
    output reg [9:0] LEDG
);

always@(posedge(CLOCK_50))

    begin
        case(SW[0])
            0:
                LEDR = 0;
            1: 
                LEDR = ~LEDR;
        endcase

        case(SW[1])
            0:
                LEDG = 0;
            1:
                LEDG = ~LEDG;
        endcase 
        case(SW[2])
            0:
                begin
                    LEDR = 0;
                    LEDG = 0;
                end
            1:
                begin
                    LEDR = ~LEDR;
                    LEDG = ~LEDG;
                end
        endcase 

    end
endmodule

Upvotes: 0

Views: 407

Answers (1)

inye
inye

Reputation: 1796

Some problems in the code are:

  1. for this situation is best with non-blocking assign. Explication 12

  2. you are reassigning LEDR and LEDG with the case(SW[2]) statement

  3. You are toggling the values of LEDG and LEDR on each posedge(CLOCK_50). this is the reason why you see low intensity in leds.

tips:

  1. you can use bit notation (also hex) like LEDG = 10'b1111111111; or LEDG = 10'b1111_1111_11; (hex: 10'h3AA)

  2. you can use a case for the SW like:

    case(SW)
    3'b000:
        ...
    3'b001:
        ...
    3'b010:
        ...
    3'b100:
        ...
    default:
        ...

Upvotes: 1

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