CODEWITHSUNDEEP
loopsasynchronousverilogsequential
Eric Johnson
Eric Johnson

Reputation: 205

Verilog loop sequentially for each iteration of the loop

I have created a module that is this:

module testX(input [6:0]n, input [6:0]offset, output result);

I want to run this module increasing the offset until result returns a specific condition. When I use a loop, the code is compiled so all of the iterations run at the same time like normally synthesized code.

I want to make testX use all the resources of the FPGA and then by changing the offset loop it multiple times in order to make a massive parallel application.

I understand that loops are not to be used like this according to this source, so how would I accomplish something like this? In a normal programming language, I would just do something like this:

while result==0
   testX(n,offset,result)
   offset=offset+C
end while

Another side question is how would I know then the testX operation is complete? Would I need a status variable to indicate it was finished and to change the offset when I saw that the status changed?

Note: This could probably be done with a clock and always statement also, but I am looking for a asynchronous method.

Upvotes: 0

Views: 1066

Answers (1)

Greg
Greg

Reputation: 19104

You need to time-plex the change to offset like below. Hardware will not function properly with complex asynchronous feedback.

always @(posedge clk) begin // time-plexing
  if (result==0) begin
     offset <= offset+C; // inside a procedural block, non-blocking assignment
  end
end

testX(n,offset,result); // outside any procedural block

Upvotes: 1

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