CODEWITHSUNDEEP
verilogiverilog
Zabitz
Zabitz

Reputation: 35

Icarus Verilog syntax error when subtracting two 32-bit inputs?

I am having a very frustrating experience with my first week learning Verilog.

I am trying to compile the below code - from mipsalu.v

module MIPSALU (ALUctl, A, B, ALUOut, Zero);
  input [3:0] ALUctl;
  input [31:0] A,B;
  output reg [31:0] ALUOut;
  output Zero;
  assign Zero = (ALUOut==0); //Zero is true if ALUOut is 0; goes anywhere
  always @(ALUctl, A, B) //reevaluate if these change
    case (ALUctl)
      0: ALUOut <= A & B;
      1: ALUOut <= A | B;
      2: ALUOut <= A + B;
      3: ALUOut <= A ^ B;
      6: ALUOut <= A – B;
      7: ALUOut <= A < B ? 1:0;
      12: ALUOut <= ~(A | B); // result is nor
      default: ALUOut <= 0; //default to 0, should not happen;
    endcase
endmodule

When I try to compile this using iverilog -o test mipsalu.v, iverilog tells me

mipsalu.v:13: syntax error
I give up.

When I remove the offending line and compile again, there are no errors-

module MIPSALU (ALUctl, A, B, ALUOut, Zero);
  input [3:0] ALUctl;
  input [31:0] A,B;
  output reg [31:0] ALUOut;
  output Zero;
  assign Zero = (ALUOut==0); //Zero is true if ALUOut is 0; goes anywhere
  always @(ALUctl, A, B) //reevaluate if these change
    case (ALUctl)
      0: ALUOut <= A & B;
      1: ALUOut <= A | B;
      2: ALUOut <= A + B;
      3: ALUOut <= A ^ B;
      //6: ALUOut <= A – B;
      7: ALUOut <= A < B ? 1:0;
      12: ALUOut <= ~(A | B); // result is nor
      default: ALUOut <= 0; //default to 0, should not happen;
    endcase
endmodule

Any insight would be much appreciated. Thank you!

Edit: it's worth mentioning that I am running version 10 of Icarus Verilog on Windows 8.1 using MinGW/MSYS

Upvotes: 3

Views: 1211

Answers (1)

Greg
Greg

Reputation: 19122

Not sure how you did it, but your – is a character in the extended ASCII under ISO 8859-1. Accrding to ascii-code.com the ASCII code number is 150 DEC (HTML code &#150;). Verilog is expecting - ASCII code number 45 DEC (HTML code &#45;).

The two look nearly identical; – (&#150;) is just a few pixels longer than - (&#45;) at least with some fonts.

It might be your text editor that is changing it on the fly, thinking the dash looks more readable then a minus.

FYI: in Verilog you usually want combinations logic to be assigned with blocking assignments (=) and sequential logic to be assigned with non-blocking assignments (<=). You are using non-blocking for combinational logic and should change to blocking.

always @(ALUctl, A, B) is legal but be aware there is also always @* (or always_comb for SystemVerilog) which is an auto-sensitivity list. If you miss an item in your sensitivity list, verilog functional behavior in simulation and synthesized functional behavior can differ.

If you want to reduce some typing, you may want to try the ANSI header style. Its been discussed several times with other questions (https://stackoverflow.com/search?q=%5Bverilog%5D+ANSI)

Upvotes: 4

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