CODEWITHSUNDEEP
verilogsystem-verilog
nashile
nashile

Reputation: 23

How to use unique statements in verilog?

I'd like to know how to use the unique statement in verilog .

for example

if (in0) se1 = 2'b00;
else if (in1) se1 = 2'b00;
else if (in2) se1 = 2'b00;
else if (in3) se1 = 2'b00;

If in0 and in1 are true then in0 is selected.

unique if (in0) se1 = 2'b00;
else if (in1) se1 = 2'b00;
else if (in2) se1 = 2'b00;
else if (in3) se1 = 2'b00;

If in0, in1 are true then how is this handled?

Upvotes: 2

Views: 4195

Answers (2)

ChetanJoshi
ChetanJoshi

Reputation: 71

First of all I want to tell you that unique feature is for system-verilog not for verilog. The SystemVerilog unique keyword can be applied to an if…else statement to convey the same uniqueness properties. For a unique if statement, a simulator will generate a run-time warning if any of the following is false:

  • If two or more of the if conditions are true at the same time.
  • If all of the if conditions (including else if) are false, and there is no final else branch.

Upvotes: 2

dave_59
dave_59

Reputation: 42788

The unique keyword added to an if or case statement does two things:

  • It adds an assertion to make sure that only one branch condition is true. The assertion is checked during simulation or by formal tools to make sure that it's not possible for more than condition to be true.
  • It tells synthesis tools to generate optimized logic with the assumption that only one branch condition can be true at a time.

If it turns out that both in0 and in1 are true, simulation will still take the first branch, but you will get an error message. The actual hardware will generate unpredictable results.

Upvotes: 3

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