CODEWITHSUNDEEP
vhdlmodelsim
JC_Onp
JC_Onp

Reputation: 45

Counter is not incremented when controlling signal changes

I implemented a simple counter 0 to 255 design in VHDL. It works as expected on the FPGA board, but when I simulate it in Modelsim, the counter does not add when I force key(0) to change. Any thoughts? 

library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

ENTITY PROC_TEST     IS
  PORT(
    CLOCK_50: IN STD_LOGIC;
    KEY: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    LEDR: OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
    );
END PROC_TEST;

ARCHITECTURE MAIN OF PROC_TEST IS
  SIGNAL COUNTER: INTEGER RANGE 0 TO 255;
BEGIN

  LEDR(7 DOWNTO 0)<= STD_LOGIC_VECTOR (TO_UNSIGNED(COUNTER,8));

  PROCESS (CLOCK_50)
  BEGIN
    IF (KEY(0)'EVENT AND KEY(0) = '0')THEN
      COUNTER<=COUNTER + 1;
    END IF;
  END PROCESS;
END MAIN;

Upvotes: 1

Views: 348

Answers (1)

Martin Zabel
Martin Zabel

Reputation: 3659

The signal KEY(0) is missing in the process sensitivity list. This is typically indicated by a warning, when you synthesize your code for an FPGA.

A process only executes/resumes:

  • once after simulation startup,
  • whenever one of the signals in the sensitivity list changes.

Thus your process only executes when CLOCK_50 is changing, but not when you force a change on KEY(0) in the simulator. Thus, you have to change your code to:

PROCESS (KEY(0))

After making this change, the simulation output is at follows with a 10 MHz clock applied to KEY(0):

simulation output

Further remarks:

As you see in my simulation screenshot, the signals LEDR(9) and LEDR(8) have an undefined ('U') value. This happens because you forgot to assign them in your architecture. This should be indicated by synthesis as well. Often the synthesizer just assign '0' (logic low) to the outputs, which can be achieved explicitly with:

LEDR(9 downto 8) <= "00";

The other input signals have an undefined value in my simulation because these are unused inputs and I have not applied any waveform to it.

Upvotes: 1

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