CODEWITHSUNDEEP
system-verilog
user3900460
user3900460

Reputation: 93

How to connect output of a module to its input?

How to tell in SystemVerilog that one of the module's outputs is directly connected to one of it's inputs?

Does it depend on the modeling level used? If yes, what is the right way for switch level?

module abc (input in1, in2, output out1, out2, out3);

// out3 needs to be directly connected to in1
// ...

endmodule

Upvotes: 0

Views: 4040

Answers (1)

dave_59
dave_59

Reputation: 42613

There are a number of ways to do this. But not all downstream tools like synthesis physical tools may support it.

This is the way to do it in SystemVerilog

module abc (input in1, in2, output out1, out2, out3);
// out3 needs to be directly connected to in1
// ...
alias out3 = in1;
endmodule

In Verilog

module abc (input .in1(sig), in2, output out1, out2, .out3(sig));
wire sig;
// out3 needs to be directly connected to in1
// ...
endmodule

Upvotes: 2

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