CODEWITHSUNDEEP
verilogsystem-verilog
haykp
haykp

Reputation: 445

Automatic Verilog code generation issue

I am trying to make the generation of FSM state parametric or automatic. I tried many ways and seems there is no way to generate the code I need. Can someone help please?

The Code which I need to generate is part of FSM state machine, for the ST_DATA_CHECK state:

always @(posedge ui_clk_sync_rst or posedge ui_clk)
  begin
    if (rst) begin
      s_app_cmd           <= 3'b111;
      s_app_en            <= 1'b0;
end
end else begin
        case (ddr3_state)
          ST_INIT :
….
          ST_DATA_CHECK :   // This part of the code, needs to make parameteric
              if (~dwfifo_ef[0]) begin
                s_data_write_active[0] <= 1'b1 ;
              end else if (~dwfifo_ef[1]) begin
                s_data_write_active[1] <= 1'b1 ;
              end else if (~dwfifo_ef[2]) begin
                s_data_write_active[2] <= 1'b1 ;
              end else if (~d_rfifo_ef[0]) begin
                s_data_read_active[0] <= 1'b1 ;
              end else if (~d_rfifo_ef[1]) begin
                s_data_read_active[1] <= 1'b1 ;
              end
          ST_WRITE :
               …
endcase

Please notice that for example dwfifo_ef[0] and dwfifo_ef[1] bits can be 0 at the same time, so that’s why I need to use priority encoder here.

Any help/idea/suggestion is welcomed about how I can make the code parametric.

Thanks Hayk

Upvotes: 0

Views: 106

Answers (2)

Matthew
Matthew

Reputation: 13937

@dave_59 has just about solved your problem, but as you say "in my if statement there are 2 signals s_data_write_active and s_data_read_active", how about trying something like this?

ST_DATA_CHECK : 
              if (|dwfifo_ef == 1'b1)
                for (int i=0;i<$bits(dwfifi_ef);i++)
                  if (~dwfifo_ef[i]) begin
                    s_data_write_active[i] <= 1'b1 ;
                    break;
                  end 
              else 
                for (int i=0;i<$bits(d_rfifo);i++)
                  if (~d_rfifo[i]) begin
                    s_data_read_active[i] <= 1'b1 ;
                    break;
                end

(I have not tried to compile, simulate or synthsise this, hence my phrase something like.)

Upvotes: 1

dave_59
dave_59

Reputation: 42616

You want a for loop with a break statement:

ST_DATA_CHECK :   
              for (int i=0;i<$bits(dwfifi_ef);i++)
              if (~dwfifo_ef[i]) begin
                s_data_write_active[i] <= 1'b1 ;
                break;
              end

Upvotes: 1

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