CODEWITHSUNDEEP
vhdl
Zac Uwyo H
Zac Uwyo H

Reputation: 147

Vhdl signal declaration usage

I am a beginner in vhdl with not much grasp on signal.

My understanding is you can assign signal value such as signal<='100' but you don't have to declare it. Is that correct?

Also, for sign extension ext_imme<=(31 downto 16=> imme(15)) & imme; why would this work for extending 16 bit to 32 bit by repeating imme(15) twice?

Upvotes: 1

Views: 2396

Answers (1)

Matthew
Matthew

Reputation: 13967

1) You can not assign signal value such as signal<='100' without declaring it it. You are not correct.

VHDL doesn't like surprises. Everything always must be declared before you use it.

So, you must declare a signal (in the declarative region of the architecture, ie between architecture and begin):

architecture SOME_NAME of SOME_OTHER_NAME is
  -- declare signals (and other things) here, eg
  signal SOME_SIGNAL_NAME : std_logic;  -- or some other type
begin

You can also initialise signals when you declare them, but I would be very careful doing this if you intend to synthesise the code, eg:

  signal SOME_SIGNAL_NAME : std_logic := '0';

2) This ext_imme<=(31 downto 16=> imme(15)) & imme is an example of an aggregate and a concatenation. An aggregate is a way of assigning to the elements of an array. A concatenation is a way of joining two arrays together to make a bigger array.

In your example, this is the aggregate: (31 downto 16=> imme(15)). Here you are making bits 31 down to 16 equal to bit 15 of imme. This gives you 16 bits all equal to bit 15 of imme.

The '&' operation is the concatenation operator. In your example, you are joining the 16 bits of the aggregate to the 16 bits of imme to make 32 bits in total.

Here some other examples of using aggregates: http://www.edaplayground.com/x/CQm.

Upvotes: 2

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