CODEWITHSUNDEEP
assemblymipscpu-registerscpu-architecture
Bwoods
Bwoods

Reputation: 187

What does the offset do in this line of MIPS code: lw $s0,4($t0)?

Not sure if the offset means fetch and store the instruction one line (4bytes) away from the 'load word's' program counter into register $s0,4($t0). How does this work in memory? Please provide examples if possible.

Upvotes: 1

Views: 21047

Answers (1)

Tetragrammaton
Tetragrammaton

Reputation: 166

The functionality of LW and SW can be read in the MIPS Instruction Set, which Michael said already.

But, to make it quick, I still provide an answer here. LW stands for Load Word. It loads a 32-bit word value to a target register (rt) from an address where this value is stored at.

LW rt, offset(base)

Let's make an easy example:

LUI T0, 0x8033
LW T1, 0x2550(T0)

The above code would now load the 32-bit word value located at address: 

0x80332550

The value in LUI is the upper half of the address, while the provided offset 0x2550 is lower half. Now MIPS simply loads the 32-bit value from 0x80332550.

Let's say 0x80332550 contains following value:

0x80332550: 25 66 99 88 77 14 22 66

After the LW instruction, T1 would now contain the value 0x25669988. (If on big-endian, on little-endian it would be 0x88996625)

SW does nearly the same like LW, just that it stores a 32-bit value to the provided address instead of loading it. The rt register acts in that case as the value-holder.

Upvotes: 7

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