CODEWITHSUNDEEP
system-verilogliterals
P_B_and_J
P_B_and_J

Reputation: 9

systemverilog: use of unsized & unbased literal in comparison

I've looked thru the LRM, haven't found a clear answer... How is the following interpreted: 

logic [7:0] data;
logic       sig_out;

assign  sig_out = (data == '1);

Will it be interpreted as:

assign sig_out = (data == 8'hFF);

Do sim & synthesis interpret this differently?

thx

PB&J

Upvotes: 0

Views: 2023

Answers (3)

stephan
stephan

Reputation: 1

'1 means all ones, so if data is 8 bit wide then data = 8'hff. If you meant to write the value 8'h01 in a context determined length way, use 'b1 which will be interpreted in this case as 8'h01.

Upvotes: 0

Karan Shah
Karan Shah

Reputation: 1992

It works as 8'hff.

Consider the below code, with it's output - 

module top();
  logic [7:0] data;
  logic       sig_out;

  assign  sig_out = (data == '1);  

  initial
    begin
      data = 'h01;
      #1 $display("sig_out - %0h", sig_out);  
      data = 'h0f;
      #1 $display("sig_out - %0h", sig_out);  
      data = 'hff;
      #1 $display("sig_out - %0h", sig_out);  
    end
endmodule

Output - 

sig_out - 0
sig_out - 0
sig_out - 1

Upvotes: 0

dave_59
dave_59

Reputation: 42623

5.7.1 Integer literal constants of the 1800-2012 LRM explains that '1 has the width of the value based on the context where it is used. When using it in a self-determined context, it has a width of 1 bit. Table 11-21 explains that the operands of relational operators in a context sized to the largest operand

So '1 in your context is 8'hff.

Upvotes: 3

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