Default statement in SystemVerilog Case

Question

I'm trying to understand following scenario:

typedef enum logic [2:0] {
   ONE, TWO, THREE, FOUR, FIVE
} enum_t;

A case statement with enum_t type in case expression:

enum_t case_expression;
logic [2:0] result;

case (case_expression)
   ONE: result = 3'b000;
   TWO: result = 3'b001;
   THREE: result = 3'b010;
   FOUR: result = 3'b011;
   FIVE: result = 3'b100;
endcase

I'm not sure or clear about following :

• Is it okay not to have a default case statement for result? The case_expression is an enum with only 5 valid values. However it's 3 bits. So how the synthesis tool will evaluate this logic? Is it going to infer latch ?
• All case items are mutually exclusive. So can I use unique keyword here to aid synthesis tool to optimize the design?

I don't have much expereince in synthesis. So I would appreciate any feedback. Thanks!

Answer 1

I believe "unique case" is a directive to synthesis tool mentioning all cases are enumerated. This would prevent a latch. If in simulation if none of the ENUM values are on the case expression, then during simulation a runtime error will be reported.

Answer 2

If "case_expression" takes the value "x", the case statement will not be able to resolve which case to enter. If default case were to be mentioned, it would gracefully enter the default case. You will see runtime error if case_expression takes value of "x" if default is not mentioned.

Answer 3

This depends on how strongly typed your synthesis tool is. Unfortunately, there are a number of ways that your case_expression could have the value 3'b111 (through casting and poor error checking in some simulation tools). So its best to put the default in for safety's sake.