CODEWITHSUNDEEP
system-verilog
Sandro Sartoni
Sandro Sartoni

Reputation: 123

Default type input and output signals SystemVerilog

I'm trying to learn by myself SystemVerilog (I'm a university student and in my projects I've always used VHDL) and I have a question concerning data types. So far, I think I understood the differences, pro and cons between reg, wire and logic but I'm wondering, in this code snippet:

module example(

input clk,
input nrst,
input nset,
input up,
input [3:0] preload,
output [3:0] counter

);

what's the default type assigned to inputs and outputs? Is it logic (as it is the best choice for "everyday" circuitry)?

Upvotes: 3

Views: 8037

Answers (1)

dave_59
dave_59

Reputation: 42616

In SystemVerilog, wire and reg/logic are closely related, but independent concepts. logic is a datatype, and wire denotes a net (or network) signal kind. There are two basic signal kinds: nets(wire) and variables(var) In a port list declaration, the default is wire logic, meaning a 1-bit 4-state net.

The defaults start to get more involved when you specify a datatype without a kind and the other way around. For inputs, the default unspecified kind is always a net, but for outputs, as soon as you specify a datatype, the default kind becomes var. Verilog appeals to lazy engineers who do not like coding. I suggest being explicit and never reyling on defaults.

I have some examples of this posted here.

Upvotes: 5

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