CODEWITHSUNDEEP
verilogsystem-veriloghdl
Xflkekw
Xflkekw

Reputation: 45

What happens if you add a default case to a full case statements?

As stated in the title, What happens if a default statement is added to a full case statement? Will this cause any issue in simulation/synthesis? If not, what is the purpose of adding this default statement to a full case?

For example,

'''
enum logic [1:0] {Reset, A, B, C} state, nstate;

always_comb
begin
    case(state)
        Reset:
            if(expr)
                nstate = A;
            else
                nstate = Reset;
        A:
            if(expr)
                nstate = B;
            else
                nstate = A;
        B:
            if(expr)
                nstate = C;
            else
                nstate = B;
        C:
            nstate = A
        
        default:
            nstate = Reset;
'''

Upvotes: 1

Views: 5926

Answers (2)

Serge
Serge

Reputation: 12344

As @mcleod_ideafix showed, there is some difference in verilog simulation. The only way it can execute the default clause is with undefined inputs to the case statement itself. As a result, the default clause only represents an undefined behavior. So, it would probably be better to have x as the next state of the state machine, meaning unknown. Your state machine should be able to recover in such a case.

default: nstate = 'x;

Also note, that case behaves in a strange way in presence of 'x' of 'z' and can give you wrong answers at simulation. You might want to look into its other siblings: casez or casex. And if your synthesis supports it, into case inside.

BTW, synthesis might not be able to figure out that you have a full case there. You might want to provide a hint. In system verilog world you should use the unique case and no default. In simulation it will generate an assertion in case you hit 'default' and for synthesis it would be a full/parallel case hint.

Upvotes: 0

mcleod_ideafix
mcleod_ideafix

Reputation: 11418

A default statement will be triggered when the current value for state is not present in any other case statement. This may happen during simulation, as some (or all) bits of state may be undetermined or high impedance.

If no default statement is provided, during simulation nstate will become a latch, keeping its previous value if the current value of state is not covered in the case block. In synthesis, a full case will behave the same, regardless of having a default statement or not, although providing a default case, specially in clocked always blocks, may help the synthesizer to decide if a clock enable feature should be used.

So, if no default statement is provided, simulation and synthesis behaviour may mismatch as simulation cover more logic levels for the case variable than synthesis.

Upvotes: 3

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