CODEWITHSUNDEEP
verilog
Deeya Lahri
Deeya Lahri

Reputation: 1

How do you manipulate input arrays in an always block (verilog)?

I'm very new to verilog and i'm just starting to understand how it works. I want to manipulate an input to a module mant[22:0], in an always block but I am not sure how to go about it.

module normalize(mant,exp,mant_norm,exp_norm);

    input [22:0]mant;
    input [7:0]exp;

    output [22:0]mant_norm;
    output [7:0]exp_norm;

    reg mantreg[22:0];
    reg count=0;

    always@(mant or exp)
    begin

    mantreg<=mant; //this gives an error
        if(mant[22]==0)
        begin

          mant<={mant[21:0],1'b0};//this also gives an error
          count<=count+1;

        end 
    end
endmodule

so i have to shift the mant register if the bit22 is zero and count the number of shifts. I am so confused about when to use reg and when to use wire and how to do the manipulation. please help let me know how to go about it.

Upvotes: 0

Views: 1272

Answers (1)

Dhaval Patel
Dhaval Patel

Reputation: 11

As you can see in your code you are assigning vector value (mant) to array of 23(mantreg). Instead you should declare mantreg as reg [22:0] mantreg (which is vector of 23 bit).

Wire type variable can not be assigned procedurally. They are used only in continues assignment. Other way around reg varible can only be procedural assigned.

For that try to read out LRM of Verilog .

Upvotes: 1

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