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vhdlvivado
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Reputation: 53

vivado displays wrong real numbers - testbench - vhdl

 variable cmp_diference : real;
 variable y_aus_tb      : real := 4.9261;
 variable log3X         : real := 4.929947e+00;
 .     
 .
 cmp_diference := y_aus_tb - log3X;
 assert cmp_diference < 0.005 report "log3X = " & real'image(log3X);
 assert cmp_diference < 0.005 report "Diference = " & real'image(cmp_diference);

So the problem is that & real'image(log3X) displays the right value at the right case in TCL, but & real'image(cmp_diference) displays: 3.252959e-03 also at the right case but wrong value... The value expacted to be displayed is ~ -0.003847...

Is there something wrong with Vivado 2016.1, or there is anything wrong that I do?

Thanks a lot!

    LIBRARY ieee;
    USE ieee.std_logic_1164.ALL;
    USE ieee.numeric_std.ALL;
    USE IEEE.MATH_REAL.ALL;

    ENTITY tb_log3X IS
    END tb_log3X;

    ARCHITECTURE behavior OF tb_log3X IS 

    BEGIN
     Test_IO : process 
         variable log3X  : real      := 0.0;
         variable x_ein_tb : integer := 0;
        variable cmp_diference : real := 0.0;
        variable y_aus_tb : real := 0.0;

     begin   
        wait for 21.2 ms; --wait for some reason
            x_ein_tb := 224;
            y_aus_tb := 4,9261;  
           -- Caclulate log3X
           log3X := (log(real(x_ein_tb)))/(log(3.0)); -- logarithm to base 3 of 224
           -- Compare log3X to Y
           cmp_diference := y_aus_tb - log3X;
           -- If diference > 0.009, generate Error message and dispaly the diference between log3X and Y
           assert cmp_diference > 0.009 report "log3X = " & real'image(log3X);
           assert cmp_diference > 0.009 report "Diference = " & real'image(cmp_diference);
      end process Test_IO;
    END;

Upvotes: 0

Views: 625

Answers (1)

user1818839
user1818839

Reputation:

It would be polite to make a complete testcase (MCVE) so that others can easily test your code without having to put unnecessary effort into it. Something like

entity tb_real is
end tb_real;

architecture basic of tb_real is
begin

process
 variable cmp_diference : real;
 variable y_aus_tb      : real := 4.9261;
 variable log3X         : real := 4.929947e+00;
begin
 report "Run process";
 cmp_diference := y_aus_tb - log3X;
 assert cmp_diference < 0.005 report "log3X = " & real'image(log3X);
 assert cmp_diference < 0.005 report "Diference = " & real'image(cmp_diference);
 report "reporting log3X = " & real'image(log3X);
 report "reporting Diference = " & real'image(cmp_diference);
 wait;
end process;

end basic;

Running it with another simulator...

$ ghdl -a tb_real.vhd
$ ghdl -e tb_real
$ ghdl -r tb_real
tb_real.vhd:12:2:@0ms:(report note): Run process
tb_real.vhd:16:2:@0ms:(report note): reporting log3X = 4.929947
tb_real.vhd:17:2:@0ms:(report note): reporting Diference = -3.847000000000377e-3

As the assert tests return true, if either of these asserts fires, something is very wrong in Vivado.

More likely some other assert somewhere else is firing, in code you didn't post - remember the MCVE? - and confusing you into thinking one of these fired.

Upvotes: 1

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