CODEWITHSUNDEEP
verilogquartusprocedural
SYM2RR
SYM2RR

Reputation: 31

Verilog Error unexpected '=', expecting identifier or type_identifier

I'm building a test bench night now, and I'm not sure how should I connect several modules I built earlier. Here's the modules I used, all of them were tested and works properly.

    counter11bit_abc ctr2(ctr_enable, ctr_clr, clk_out, counter);
    register10bit_abc dut3(clk_out, d_in, q_out);
    clk #(400) clk1(clk_enable, clk_out);
    hc85_abc dut4(a_in, b_in, ia_lt_b, ia_eq_b, ia_gt_b, qa_lt_b, qa_eq_b, qa_gt_b);

I need to connect the following ports:

    assign a_in = counter [3:0];
    assign b_in = counter [7:4];
    assign ia_lt_b = counter [8];
    assign ia_eq_b = counter [9];
    assign ia_gt_b = counter [10];
    assign d_in[0] = ia_gt_b;
    assign d_in[1] = ia_eq_b;
    assign d_in[2] = ia_lt_b;

Declaration is as followed:

    wire [9:0] d_in;
    wire [9:0] q_out;
    wire [3:0] a_in, b_in;
    wire ia_lt_b, ia_eq_b, ia_gt_b, qa_lt_b, qa_eq_b, qa_gt_b;

    reg        clk_enable;  
    reg        ctr_enable;  
    reg        ctr_clr;     
    wire       clk_out;     
    wire [10:0] counter;

For the initial part I dropped down as follow:

initial 
    clk_enable = 1;
    ctr_enable = 1;
    ctr_clr = 1;
    #400
    ctr_clr = 0;
    #1000000

Now the compiler is giving me a complain says

near "=": syntax error, unexpected '=', expecting IDENTIFIER or TYPE_IDENTIFIER

And that is for the line where "ctr_enable = 1;"

Is there anyone know what may cause this issue? I've been working on it for more than an hour trying everything I can. Thanks.

Upvotes: 0

Views: 12216

Answers (1)

nanofarad
nanofarad

Reputation: 41281

In Verilog, initial will apply to only the following statement, unless enclosed in begin/end, irrespective of indentation (since it's not Python).

As a result, your second line (ctr_enable = 1) is completely independent of the always keyword. The fix is adding begin/end:

initial begin 
    clk_enable = 1;
    ctr_enable = 1;
    ctr_clr = 1;
    #400
    ctr_clr = 0;
    #1000000;
end

Upvotes: 2

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