I'm trying to make a 8bit 4-1 selector circuit using vhdl. can someone help me what's wrong with this code?

Question

this is the vhdl code. this one has no error

library IEEE;
use IEEE.std_logic_1164.all;

entity sel4_1 is
   port( A, B, C, D : in std_logic;
     SEL        : in std_logic_vector(1 downto 0);
     outsgnl    : out std_logic );
   end sel4_1;

architecture EX1 of sel4_1 is
begin

process(A, B, C, D, SEL)
begin
case SEL is
   when "00" => outsgnl <= A;
   when "01" => outsgnl <= B;
   when "10" => outsgnl <= C;
   when others => outsgnl <= D;
end case;
end process;

end EX1;

---

this is the testbench which has the error

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity TESTBENCH is
end TESTBENCH;

architecture RTL of TESTBENCH is

component sel4_1

   port(A,B,C,D : in std_logic_vector(7 downto 0);
        outsgnl : out std_logic);

end component;

signal INA, INB, INC, IND, OUTSGNL : std_logic_vector(7 downto 0);
signal SEL : std_logic_vector(1 downto 0);

begin
   U0: sel4_1 port map(INA, INB, INC, IND, SEL, OUTSGNL);
   process
   begin
     INA <= "11111111";
     INB <= "11110000";
     INC <= "00001111";
     IND <= "00000000";

     SEL <= "00"; wait for 10 ns;
     SEL <= "01"; wait for 10 ns;
     SEL <= "10"; wait for 10 ns;
     SEL <= "11"; wait for 10 ns;

     wait;
   end process;
end RTL;

the error that came out is testbench.vhdl:19:27: can't associate 'ina' with signal interface "ina"

testbench.vhdl:19:27: (type of 'ina' is std_logic)

testbench.vhdl:11:9: (type of signal interface "ina" is a subtype of std_logic_vector)

Answer 1

As an alternative to Hakim's (perfectly correct) suggestion, there is a concurrent way to do the same thing.

library IEEE;
use IEEE.std_logic_1164.all;

entity sel4_1 is
   port( A, B, C, D : in std_logic_vector(7 downto 0);
        SEL         : in std_logic_vector(1 downto 0);
        outsgnl     : out std_logic_vector(7 downto 0) );
   end sel4_1;

architecture EX1 of sel4_1 is
begin

  with SEL select
    outsgnl <= A when "00",
               B when "01",
               C when "10",
               D when others;
end EX1;

I prefer to avoid processes for anything other than clocked processes. A missing signal in the sensitivity list will lead to simulation/synthesis mismatches. And maintaining those sensitivity lists can become a bear. And if there is a need for a combination process, the list should be very small. (And, yes, there is VHDL-2008's all, which helps.)

Answer 2

this is the code after making some corrections:

library IEEE;
use IEEE.std_logic_1164.all;

entity sel4_1 is
   port( A, B, C, D : in std_logic_vector(7 downto 0);
        SEL         : in std_logic_vector(1 downto 0);
        outsgnl     : out std_logic_vector(7 downto 0) );
   end sel4_1;

architecture EX1 of sel4_1 is
begin

process(A, B, C, D, SEL)
begin
case SEL is
   when "00" => outsgnl <= A;
   when "01" => outsgnl <= B;
   when "10" => outsgnl <= C;
   when others => outsgnl <= D;
end case;
end process;

end EX1;

---

testbench:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity TESTBENCH is
end TESTBENCH;

architecture RTL of TESTBENCH is

component sel4_1
   port(A,B,C,D : in std_logic_vector(7 downto 0);
        SEL     : in std_logic_vector(1 downto 0);
        OUTSGNL : out std_logic_vector(7 downto 0));
end component;

signal INA, INB, INC, IND, OUTSGNL : std_logic_vector(7 downto 0);
signal SEL : std_logic_vector(1 downto 0);

begin
   U0: sel4_1 port map(INA, INB, INC, IND, SEL, OUTSGNL);
   process
   begin
     INA <= "11111111";
     INB <= "11110000";
     INC <= "00001111";
     IND <= "00000000";

     SEL <= "00"; wait for 10 ns;
     SEL <= "01"; wait for 10 ns;
     SEL <= "10"; wait for 10 ns;
     SEL <= "11"; wait for 10 ns;

     wait;
   end process;
end RTL;

Answer 3

The problem is that your entity sel4_1and your component sel_4_1 are not the same. Your A,B,C,D ports are std_logic in the first one but std_logic_vector(7 downto 0) in the second one.

Change the entity (or component) with what you really need and it should work properly.