CODEWITHSUNDEEP
system-verilog
Hida
Hida

Reputation: 798

Casting unidimensional "multidimensional" array to unidimensional

We have an array (in an SVI in_apbBus) declared as:

logic [SIZE-1:0][APB_AW-1:0] apbPAddr;

When instantiating this with SIZE = 1 is this an allowed assignment?

logic [APB_AW-1:0] apbPAddr;
in_apbBus #(.SIZE(1), .APB_AW(APB_AW)) uin_apbBus();

apbPAddr = uin_apbBus.apbPAddr;

I am in theory assigning a unidimensional array an multidimensional value. However, the size of one of the inner dimension is 1 and i expect this to work for a packed array.

I get intermittent issues with these types of assignments. It seems to mostly work in QuestaSim, however when the SVI(uin_apbBus) is passed through a module hierarchy (with the receiving module inheriting the APB_AW from the interface) something goes wrong and the APB_AW for uin_apbBus seems to use the default value for APB_AW(32).

If i assign like this:

apbPAddr = uin_apbBus.apbPAddr[0];

the issue is resolved. So to eloborate on my question above: how is this defined in the LRM, and is this a tool issue?

Upvotes: 2

Views: 265

Answers (1)

dave_59
dave_59

Reputation: 42698

When dealing with packed arrays, there is no type safety in assignments between arrays of different sizes or dimensions. They are all treated as integral values that are padded or truncated to fit. How SystemVerilog treats the range [0:0] is not clearly defined in the LRM, but most tools treat it the same as if it was not specified.

The problem with APB_AW not being overwritten correctly is a separate issue that you will probably have to show a more complete testcase to the tool vendor.

Upvotes: 2

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