CODEWITHSUNDEEP
system-verilog
Jonathan Drolet
Jonathan Drolet

Reputation: 3388

How to assign an unpacked array of real?

While updating Modelsim from 10.3c to 10.6a, I encountered an error on this piece of code that used to not work without warning:

module test(
    input bit clk,
    input bit signed[31:0] data
);

    real rdata_dl[19:0] = '{20{0}};
    real rdata = 0;

    always @(posedge clk) begin
        rdata_dl = {rdata_dl[18:0], rdata};
        rdata = data;
    end

endmodule

-- Compiling module test

** Note: test.sv(10): (vlog-13177) Promoting concatenation '{rdata_dl[18:0],rdata}' to an assignment pattern: Assigning to a real/wreal array.

** Error (suppressible): (vlog-13215) test.sv(10): Assignment pattern element 'rdata_dl[18:0]': Cannot assign an unpacked type 'real $[18:0]' to a packed type 'real'.

** Error (suppressible): test.sv(10): (vlog-13174) Illegal assignment pattern. The number of elements (2) doesn't match with the type's width (20).

I managed to fix it by using this line instead: rdata_dl = {rdata_dl[18:0], real'(rdata)};.

However, I fail to understand why it failed and why the new version would work. Can anyone explain?

Upvotes: 2

Views: 2865

Answers (1)

Hagai Naveh
Hagai Naveh

Reputation: 63

not sure what you are trying to do with this code. real type is 64-bit. When concatenating it with 19-bits, you're getting a 83-bit bus, where the rdata is in the LSBs. Now, when assigning this 83-bit vector to a 20-bit bus, it will take the 20 LSBs, meaning that it is equivalent to writing the following assignment:

always @(posedge clk) begin
    rdata_dl = rdata[19:0];
    rdata = data;
end

Upvotes: 1

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