Makefile produces error "No rule to make target"

Question

I've tried to fix this using the other two most relevant topics: Makefile error: No rule to make target Makefile: No rule to make target. Stop

But neither seem to solve my issue.

I'm unsure where my code went wrong, as my instructor verified that the code works on his end.

The code for my makefile is:

TARGET  = demo
FILES   = test.c
OBJS    = $(FILES:.c=.o)
ASMS    = $(FILES:.c=.s)

all:    $(TARGET)

$(TARGET):  $(OBJS)
    gcc -o $@ $^

%.o:    %.c
    gcc -c $< -o $@

%.s:    %.c
    gcc -S -masm=intel $< -o $@

asm:    $(ASMS)

run:    $(TARGET)
    ./$(TARGET)

clean:
    rm -f $(TARGET) $(OBJS) $(ASMS)

However, when I attempt to do "make run" it produces the result

make: *** No rule to make target 'run'. Stop.

As seen here image

The actual code to my program that I'm trying to compile is only 4 lines long. I don't think it's the reason for the issue

#include <stdio.h>
char *msg = "Exam Lab 1";

int main(int argc, char *argv[]) {
    printf("%s\n", msg);
}

Here's the contents of the directory I'm running make from:

Answer 1

In my case, the Makefile depends on another external *.a library file to be already built and exist.

I mean, in Makefile-world even said external dependency is called "target".

Hence, there really is "no rule to make target" ;-)

Answer 2

From the image you've provided it's clear that you've named the file Makefile.txt. As @dbush says, the makefile MUST be named either Makefile or makefile. Those are the only file names make looks for by default.

Either that or you have to run make -f Makefile.txt.

Answer 3

Your makefile doesn't have the correct name.

By default, make looks for a file named either makefile or Makefile. Yours is named Makefile.txt, so make can't find it.

Either change the name to makefile or Makefile, or use the -f option to specify the makefile name, ex. make -f Makefile.txt.