CODEWITHSUNDEEP
system-verilog
Vivek
Vivek

Reputation: 21

SystemVerilog: How to create an interface which is an array of a simpler interfaces with different inputs?

What is the best way to create the below logic?

interface top_if(input rst_n[NUM_OF_modules],
                input clk[NUM_OF_modules]);

simple_if i_simple_if[NUM_OF_modules](.reset_n(rst_n[?]), .clock(clk[?]));

I need to send the rst_n[x] and clk[x] to corresponding i_simple_if[x]? what is the best way to do that. The reset_n and clock are 1 bit input signals of simple_if.

endinterface

Upvotes: 0

Views: 837

Answers (2)

Vivek
Vivek

Reputation: 21

I tried two different methods: 1) generate loop for the Interface : simple_if inside the top_if.The VCS is not happy about it and throwing Illegally connected interface port, when i pass the generated interface to a module. 2) So i had to try the below method.

interface top_if #(parameter NUM_OF_modules = 1) 
              (input rst_n[NUM_OF_modules],clk[NUM_OF_modules]);

   simple_if i_simple_if[NUM_OF_modules]();
endinterface
top_if i_top_if();
generate
for (genvar i=0; i<NUM_OF_modules; i++) begin
assign i_top_if.i_simple_if[i].rst_n = xxx;
assign i_top_if.i_simple_if[i].clk   = yyy;
end
endgenerate

Upvotes: 1

Matthew
Matthew

Reputation: 13967

How about a generate loop:

interface top_if #(parameter NUM_OF_modules = 1) 
                  (input rst_n[NUM_OF_modules],
                   input clk[NUM_OF_modules]);

  generate
    genvar i;
    for (i=0; i<NUM_OF_modules; i++)
      begin : NAME
        simple_if i_simple_if(.reset_n(rst_n[i]), .clock(clk[i]));
      end
  endgenerate

endinterface

http://www.edaplayground.com/x/3ALC

Upvotes: 1

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