CODEWITHSUNDEEP
makefile
sumit
sumit

Reputation: 141

Not able to understand the use of .suffixes rule in makefile ubuntu

I have seen various makefiles where they use the .SUFFIXES rule. As per my understanding which means, taking a simple example

step1: 

.SUFFIXES: .o .c .cpp .cc .cxx .C

#where $< indicates the source file and $@ represents the target file.
.cpp.o:
        $(CXX) -c $(INCPATH) -o "$@" "$<"

it will compile the target file to a .o file using the source with CXX compiler.

But after this i also see some other commands like

step2: 

all: Makefile $(TARGET)

Step3: 

someobjectfile.o: dependencies

So, if we can use .SUFFIXES rule to compile my target then why to use Step3. i apologies if it is a silly question.

Upvotes: 2

Views: 989

Answers (2)

Maxim Egorushkin
Maxim Egorushkin

Reputation: 136515

.SUFFIXES controls suffix rules:

Suffix rules are the old-fashioned way of defining implicit rules for make. Suffix rules are obsolete because pattern rules are more general and clearer. They are supported in GNU make for compatibility with old makefiles.

In other words, you can ignore .SUFFIXES and write your pattern rule as:

%.o : %.cpp

someobjectfile.o: dependencies

The above adds dependencies of someobjectfile.o regardless of how .o are made.

Upvotes: 1

user657267
user657267

Reputation: 21040

I'll start off by pointing out that suffix rules are obsolete in GNU make

Suffix rules are the old-fashioned way of defining implicit rules for make. Suffix rules are obsolete because pattern rules are more general and clearer. They are supported in GNU make for compatibility with old makefiles.

(Although for legacy reasons .SUFFIXES still controls which built-in rules will be available.)

That said, just because you've told make that .o files can be compiled from sources with certain suffixes does not mean that there aren't any other dependencies beyond the individual source file, the following is extremely common for example

someobjectfile.o: someheader.h someotherheader.h

Upvotes: 1

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