CODEWITHSUNDEEP
castingintlogicsystem-verilog
Brian Crafton
Brian Crafton

Reputation: 476

System Verilog: Casting from logic to int

I am trying to cast a 'logic [2:0]' type to an integer in system verilog. It took me awhile to realize this was the problem why my test was not working as expected.

I was trying to cast it like this:

int a = int '(signal);

Where signal is a logic [2:0]. But this was always assigning a as 0.

Currently this code:

     int a;
     if(signal=== 3'b000) begin
        a = 0;
     end else if(signal=== 3'b001) begin
        a = 1;
     end else if(signal=== 3'b010) begin
        a = 2;
     end else if(signal=== 3'b011) begin
        a = 3;
     end else begin
        assert(0);
     end

works but I would really like to be able to cast this type.

I really could not find this addressed in ANY sites, book, or stackoverflow thread so if someone finds a duplicate I will be thoroughly embarrassed

Upvotes: 1

Views: 22432

Answers (1)

dave_59
dave_59

Reputation: 42698

You should not need a cast to go from logic to int. SystemVerilog implicitly casts all integral types. The only issue is if a bit in your signal is set to X or Z, then the value gets converted to 0. What you probably want to do is

assert (!$isunknown(signal))
       a = signal;
else
  $error("signal is unknown");

Upvotes: 6

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