CODEWITHSUNDEEP
system-verilogpreprocessor-directive
Elena Hammari
Elena Hammari

Reputation: 1

SystemVerilog: is it possible to make `define based on value of a package parameter?

Is it possible to specify a `define parameter based on a value of a package parameter? F.ex:

if(pa_ProductSetup::MODULE_SET=="A") 
`define MODULE_A_INCLUDED

And use it later to select which parts of the code to compile:?

`ifdef(MODULE_A_INCLUDED)

`endif

Best regards,

Elena H.

Upvotes: 0

Views: 1145

Answers (1)

dave_59
dave_59

Reputation: 42723

No, you can't do this. Preprocessor directives are parsed before any other SystemVerilog syntax. You can use generate-if blocks to control what gets compiled, but generate block are much more restricted as far as what is allowed inside them

if (pa_ProductSetup::MODULE_SET=="A") begin :generate_block
// put the code here you would have wanted inside the `ifdef
end :generate_block

Upvotes: 1

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