CODEWITHSUNDEEP
verilogsystem-verilog
Jonathan Mayer
Jonathan Mayer

Reputation: 1482

Can the preprocessor tell if SystemVerilog is enabled?

I'd like to be able to write code like this:

`ifdef SYSTEMVERILOG_ENABLED
  .. systemverilog code here.
`else
 .. verilog-2001 equivalent code here.
`endif

But the SystemVerilog reference manual doesn't seem to reference any such standard predefined constant. This seems like an oversight -- is there a simple way to do what I intend here?

Upvotes: 1

Views: 758

Answers (1)

dwikle
dwikle

Reputation: 6978

Yes, there are compiler directives begin_keywords "version_specifier" and end_keywords, where:

version_specifier ::=
    1800-2009
  | 1800-2005
  | 1364-2005
  | 1364-2001
  | 1364-2001-noconfig
  | 1364-1995

Example from the LRM:

`begin_keywords "1364-2001" // use IEEE Std 1364-2001 Verilog keywords
module m2 (...);
reg [63:0] logic; // OK: "logic" is not a keyword in 1364-2001
...
endmodule
`end_keywords

This is covered in chapter 22.14 of IEEE 1800-2009.

Personally, I've never used these so I have no idea how well the tools support them.

Upvotes: 4

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