CODEWITHSUNDEEP
system-verilog
maskarih
maskarih

Reputation: 867

Random WIDTH mask in SystemVerilog

I am trying to create a random width bit mask. I have an array of 256 bits and every 32 bits correspond to a channel (8 channels in total). I need to generate a Mask that can randomly select channels from 0 to 7.

`define CHANNELS    8
`define INPUT_WIDTH 256 
...
logic [`INPUT_WIDTH -1:0] input_data ='{default:1'b0};
int num_channels                     = $urandom_range(0,`CHANNELS-1);

So if num_channels is 4, it means I need a mask that has the same number of bits as my input_data but has 4*32 ones at the beginning so: 

const int MASK_WIDTH = num_channels*`CHANNELS;

I was hoping to use SystemVerilog replication feature to create the mask as below:

logic [`INPUT_WIDTH -1:0] mask
mask = '{MASK_WIDTH{1}};

but I get the following error: Illegal operand for constant expression [4(IEEE)].

Which kind of make sense. Since I cannot use a dynamic packed array, I am only left with this solution:

for (int i = 0; i < MASK_WIDTH; i++) 
    mask [i]=1'b1;

which is super ugly. I am wondering if there is a better solution?

Upvotes: 2

Views: 1728

Answers (1)

dave_59
dave_59

Reputation: 42623

mask = 1'b1
mask = (mask << MASK_WIDTH) -1;

Upvotes: 4

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