CODEWITHSUNDEEP
system-veriloguvm
Ashutosh Rawal
Ashutosh Rawal

Reputation: 301

uvm_event and system verilog event difference

What is the advantage of uvm_event over the SystemVerilog event ? Can someone explain with small pseudo code ?

Upvotes: 5

Views: 4769

Answers (2)

dave_59
dave_59

Reputation: 42698

There are no advantages of using uvm_event over what is in the basic SystemVerilog event construct unless you need the extra functionality provided by the uvm_event The additional features include adding a uvm_object to be associated with the trigger, and booking information like keeping track of the number of waiters and the last time the uvm_event was triggered.

I have not seen much use for these additional features, and events in general are usually too low level for most testbenches to be dealing with.

Upvotes: 4

sharvil111
sharvil111

Reputation: 4381

UVM is nothing but a wrapper library developed over SystemVerilog. So, the uvm_event and SystemVerilog events are the same but uvm_event has some additional functionality.

From the UVM Class reference:

The uvm_event class is a wrapper class around the SystemVerilog event construct. It provides some additional services such as setting callbacks and maintaining the number of waiters.

A traditional Systemverilog event does not have functionality to pass data when event is triggered. While uvm_event adds this functionality. So, you can pass the transaction class handle when some event is triggered.

Just like traditional SV events, uvm_event also has trigger and persistent trigger modes (while SV has wait(ev.triggered) and @(ev) counterparts).

You can also add callbacks whenever an event is triggered. This is done by registering a callback class with particular event.

As far as events are concerned, they seem to be costly in terms of overhead. You can get many examples on uvm_event like this one.

Upvotes: 6

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