CODEWITHSUNDEEP
llvmvectorizationllvm-irllvm-c++-api
DTharun
DTharun

Reputation: 786

What SELECT instruction lowers to in ISA?

While vectorizing if the loop contains 'if constructs' llvm tries to flatten them by replacing with SELECT instructions to make the control flow straight, if the basic blocks cannot be turned to predicated instructions like SELECT, llvm can't vectorize it. Till now am assuming that there should be some equivalent instruction for SELECT like IR instructions. I searched for predicated instruction in intel architecture I din't got any. Can someone please tell me does current ISA architectures support predicated instructions? If not, How the SELECT instructions will be lowered into machine instructions? Please correct me if I have made any wrong assumptions.

Thanks in advance

Upvotes: 2

Views: 725

Answers (1)

A. K.
A. K.

Reputation: 38098

Yes several architectures support conditional/predicated execution. For example ARM has csel AArch64 ISA.

It is quite common in VLIW architectures because they need to fill the packets. Predicated execution

Upvotes: 1

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